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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Not Answered

    armRAL.h library in arm cortex -A9 0

    • Cortex-A9
    1202 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Suggested Answer

    FP4 datatype support on Cortex-M FPU? 0

    1577 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cortex M4 - Access Level 0

    • Cortex-M4
    3694 views
    3 replies
    Latest over 2 years ago
    by Sudhu145
  • Not Answered

    TLB Broadcast serialization 0

    • AArch64
    • System architectures
    1789 views
    2 replies
    Latest over 2 years ago
    by ashmog Arm Employee Badge
  • Suggested Answer

    Interrupt servicing order on later arrived high priority interrupt with same subgroup. 0

    • Armv8-M
    1245 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    data coherency when NIC and CCI both used to access DDR 0

    789 views
    0 replies
    Started over 2 years ago
    by qp.harson
  • Suggested Answer

    Bare metal - EL2 to EL1 - SP behaviour 0

    4261 views
    7 replies
    Latest over 2 years ago
    by Chaudhary Shehwar Hussain
  • Answered

    Possible Documentation error in KBA Article ID: KA001775? +1

    • Documentation
    • PrimeCell DMA Controller (PL081)
    2110 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Can BLAS lib been used on Cortex-A9 based SOC baremetal system? 0

    • Cortex-A9
    • SoC FPGA
    1671 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Suggested Answer

    ARM R5F Static Registers 0

    1464 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    What should be LR(link register) value for Cortex-M7 core? 0

    • Cortex-M7
    • Cortex-M
    3867 views
    2 replies
    Latest over 2 years ago
    by TS_Sanshin
  • Not Answered

    Can I enchance Rreadnosnoop to accept dirty line? 0

    • ACE
    909 views
    0 replies
    Started over 2 years ago
    by luffy.bright
  • Not Answered

    Cortex-A53 Data Cache line allocation without reading memory 0

    • Cortex-A53
    • Armv8-A
    • Cache Management
    2981 views
    2 replies
    Latest over 2 years ago
    by Tapir
  • Suggested Answer

    Cortex R5 ARM processor 0

    • Cortex-R5
    9762 views
    13 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    [ATSAM3X8E] ADC Read thought process 0

    • Arduino Due
    737 views
    0 replies
    Started over 2 years ago
    by CedricAve1
  • Not Answered

    Define last transaction in CHI protocol 0

    • CHI
    924 views
    0 replies
    Started over 2 years ago
    by thinhduynguyen
  • Not Answered

    How to "clear" the source of dtb from video devices. 0

    866 views
    0 replies
    Started over 2 years ago
    by ziomario
  • Suggested Answer

    Armv7-M and Cortex-M3 0

    • Armv7-M
    • Cortex-M3
    2917 views
    1 reply
    Latest over 2 years ago
    by Siyu Mou Arm Employee Badge
  • Not Answered

    What is the need of EMPTY state of cache in the CHI protocol 0

    895 views
    0 replies
    Started over 2 years ago
    by GVK
  • Not Answered

    Using the WFI command on STM32U599 and IRQ pending 0

    1256 views
    1 reply
    Latest over 2 years ago
    by Angie Whiteley
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