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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3636 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8811 views
    0 replies
    Started over 5 years ago
    by Annie
  • Suggested Answer

    Bit Trimming - A New Approach For The Optimization of Thumb 32-Bit x 32-Bit --> (top) 32-bit Calculations 0

    • Cortex-M0
    • Cortex-M0+
    173 views
    3 replies
    Latest 1 day ago
    by Sean Dunlevy
  • Not Answered

    Potential Issue in ARM7TDMI Documentation 0

    • Arm7tdmi
    • Documentation
    161 views
    1 reply
    Latest 4 days ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Realtime differences between Cortex-R and M and Hardware Features 0

    • Cortex-R52
    • Architecture
    • Cortex-R
    • Cortex-M7
    • Cortex-R5
    • Real-Time
    • Cortex-M
    • Cortex-M33
    433 views
    1 reply
    Latest 5 days ago
    by Paul Sigmon Arm Employee Badge
  • Not Answered

    AMBA CHI bus atomics + ARM core implementation for big-endian 0

    118 views
    0 replies
    Started 8 days ago
    by Shane Lardinois
  • Suggested Answer

    Question about CHI spec:Issue about the Relationship Between TxnID and ReturnTxnID for HN DMT=0 ReadNoSnp Transaction 0

    330 views
    1 reply
    Latest 16 days ago
    by Cecilia Cheng Arm Employee Badge
  • Suggested Answer

    Synchronous FPU Exception in Cortex R5 0

    • Cortex-R5
    249 views
    1 reply
    Latest 23 days ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    From Free Bird to Jailbird: The Physical Shackle for Agentic AI. Hardware-enforced AI confinement via ARMv9-A CCA. 0

    535 views
    2 replies
    Latest 26 days ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    ​[UPDATE] Guardian Angæl Protocol (GAP) V1.1 — Billion-Cycle Validation Results 0

    428 views
    1 reply
    Latest 29 days ago
    by Alexander Colclough
  • Not Answered

    MBIST test L1 and L2 cache 0

    229 views
    0 replies
    Started 29 days ago
    by Ping L_0941
  • Not Answered

    Processor has escalated a configurable-priority exception to HardFault 0

    431 views
    0 replies
    Started 1 month ago
    by Aakash Tegginamani
  • Not Answered

    ECC Test for A53 Cache memories 0

    • Cortex-A53
    • Cache Architecture
    369 views
    0 replies
    Started 1 month ago
    by Nihar Potturu
  • Not Answered

    CFP RCTX instruction on Neoverse-N3 0

    • EL1
    • AArch64
    • Security
    • Neoverse
    • Branch Prediction
    257 views
    0 replies
    Started 1 month ago
    by Gal Kaptsenel
  • Answered

    Cortex-M85 & Cortex-M55 Core ID 0

    • Cortex-M55
    • Cortex-M85
    1447 views
    3 replies
    Latest 1 month ago
    by Mahmood Yakub Arm Employee Badge
  • Suggested Answer

    AXI5 0

    • AMBA 5
    373 views
    2 replies
    Latest 1 month ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Dormant state for debug 0

    • Debugging
    388 views
    0 replies
    Started 1 month ago
    by Yael Kanter-Weisman
  • Not Answered

    the issue of different execution times for the same assembly code on Cortex-A53 0

    917 views
    4 replies
    Latest 2 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Question about Snoop Response for SnpCleanShared using CHIE.b? 0

    • CHI
    328 views
    1 reply
    Latest 2 months ago
    by Ben Hicks Arm Employee Badge
  • Suggested Answer

    Does TCM configured as Strongly ordered memory have alignment alignment requirements? 0

    • Cortex-R5
    457 views
    3 replies
    Latest 2 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How AXI Handle unaligned transfer in FIX and INCR mode. 0

    518 views
    2 replies
    Latest 2 months ago
    by roshan ekre
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