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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3596 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8587 views
    0 replies
    Started over 5 years ago
    by Annie
  • Not Answered

    AFREADY reset value of ATB master I/F in CSTFunnel is 1'b0 0

    18 views
    0 replies
    Started 5 hours ago
    by Nakhyeon Kim
  • Not Answered

    PMU IRQ-exception counts on Cortex-A76 overcount by EL2 timer amount — enabling EL2 counting makes it increase again (RK3588) 0

    • Cortex-A76
    • 12 (Debug Monitor)
    • Cortex-A55
    130 views
    0 replies
    Started 1 day ago
    by kw z
  • Not Answered

    "Test Target" instructions - only consider SAU / IDAU, or also PPC & MPC 0

    782 views
    1 reply
    Latest 13 days ago
    by ArmMadeMeCreateAName
  • Answered

    the AMBA AHB bus master interface to start a burst with only 1 data transfer without the HSEL signal 0

    • AHB
    171 views
    1 reply
    Latest 22 days ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    APB 0

    • APB
    150 views
    1 reply
    Latest 22 days ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Is it normal that DC CVAC does also carry out a cache line invalidate on Cortex-A53? 0

    • Cache coherency
    208 views
    2 replies
    Latest 22 days ago
    by Mario Trams
  • Answered

    Cortex-R52+ mode switch 0

    • Cortex-R52+
    330 views
    3 replies
    Latest 30 days ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    More details on CSV2 0

    • Security
    • Branch Prediction
    607 views
    1 reply
    Latest 1 month ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Unable to write to memory region marked as both writable and executable on cortex-R82 0

    • Cortex-R82
    • Memory Architecture
    447 views
    5 replies
    Latest 1 month ago
    by HamzaF
  • Not Answered

    M0 GPIO level-sensitive interrupt, how many minimal CPU cycles? 0

    • Cortex-M0
    • Interrupt Handling
    147 views
    0 replies
    Started 1 month ago
    by Liudr
  • Suggested Answer

    Number of outstanding transactions in AXI 0

    • performance
    • AXI4
    • interconnect
    377 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Correctly invalidating Cortex-A53 shared L2 cache for access through ACP? +1

    • Cortex-A53
    • Cache coherency
    • AXI4
    • Cache Management
    • Cache Architecture
    390 views
    2 replies
    Latest 1 month ago
    by Dylan Barrie
  • Suggested Answer

    clarifications about ARCACHE bits in AXI4 0

    507 views
    2 replies
    Latest 1 month ago
    by Srilakshmi beeram
  • Answered

    Shift right instruction 0

    • AArch64
    476 views
    2 replies
    Latest 1 month ago
    by Eduard Kachalov
  • Not Answered

    How to implement divide with MVE intrinsic (Cortex M85) 0

    • Helium
    • MVE Intrinsics
    • Armv8.1-M
    280 views
    1 reply
    Latest 1 month ago
    by fjpmbb
  • Suggested Answer

    The behaviour of writenosnp and readnosnp that require request order in CHI 0

    415 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    axi ID problem 0

    323 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    what is difference between read unique and clean unique? 0

    328 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Setting up cache coherent transactions using CCI-500 0

    • Cortex-A72
    • Cache coherency
    • ACE
    • ACE-Lite
    • CoreLink CCI-500 Cache Coherent Interconnect
    328 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
>
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