SoC Design and Simulation forum

The Inventors Challenge Ceremony 2022

Background Arm and All India Council for Technical Education have academic partnership and signed…

Apurva Varma
The Inventors Challenge: semifinalists details

Serial Number Faculty Name Name of the students in the Team Institute Name Name of the…

Suriya Gunasekaran
Evaluation Criteria for Idea Submission - Inventors…

Please find the evaluation criteria below. You can download the criteria at the end of this post. If…

Apurva Varma
Evaluation team profiles

Alok Mittal Senior Group Manager SRA, Innovation and Collaborations – APAC STMicroelectronics…

Oliver Beirne

SoC Design and Simulation forum

Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
Threads 634 Questions

Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

Other forums

Not Answered

To PIL or not to PIL 0

40 views

0 replies

Started 7 hours ago
by tjones95134
Not Answered
How does QoS work with priority and ordering? 0
- AMBA 3 AXI Interface
- AXI4
69 views

0 replies

Started 6 days ago
by ele
Not Answered
fault_s signal holds unknown value at power-up 0
- Cortex-R5
79 views

0 replies

Started 12 days ago
by ele
Answered

1kB boundary concept in AHB 0

469 views

2 replies

Latest 27 days ago
by Almailtu
Not Answered
AMBA Low power interface relation with QACTIVE, QDENY and PWAKEUP 0
- AMBA
511 views

3 replies

Latest 28 days ago
by Annie
Not Answered
Regarding Strobe IN AXI4 0
- AXI4
316 views

1 reply

Latest 1 month ago
by Colin Campbell
Suggested Answer

Does APB allow multiple beats in a transfer like AXI/AHB? 0

316 views

1 reply

Latest 1 month ago
by Colin Campbell
Answered
The reason why AHB Slave has HREADY input and output both 0
857 views

3 replies

Latest 1 month ago
by Colin Campbell
Suggested Answer
single clock edge operation in AMBA AHB? 0
- AMBA
- AMBA 2
- AHB
314 views

1 reply

Latest 1 month ago
by Colin Campbell
Not Answered

scenario for PO&POE on ARM Artiasn GPIO ? 0

206 views

0 replies

Started 1 month ago
by yfb
Not Answered

the scenarios for fail-safe ，retention and core down on GPIO? 0

189 views

0 replies

Started 1 month ago
by yfb
Not Answered
NIC400 Axi4 Limit total number of outstanding transactions to 1 0
- AXI4
179 views

0 replies

Started 1 month ago
by hasansatana
Not Answered
The cyclone v soc GIC interrupt priority issues 0
- GIC-390 PrimeCell PL390
- Cortex-A
168 views

0 replies

Started 1 month ago
by Chun Alex
Suggested Answer
What is the CHI Interface equivalent for AXI's AxPROT[privilege] bit? 0
- AMBA 5 CHI
533 views

2 replies

Latest 2 months ago
by Chittawat P.
Suggested Answer
Query regarding AMBA AHB Subordinate responses 0
- AHB
363 views

1 reply

Latest 2 months ago
by Colin Campbell
Suggested Answer
WRAP CALCULATION in AHB LITE 0
- AMBA
- AMBA Specifications
- AHB-Lite
- AHB5
- AHB
606 views

3 replies

Latest 2 months ago
by Colin Campbell
Not Answered
Cortex M0+ CM0PINTEGRATION JTAG Integration and Simulation +1
- JTAG
- Cortex-M0+
256 views

0 replies

Started 2 months ago
by Vijayvithal
Not Answered
CHI-B Interface user sideband 0
- AMBA 5 CHI
190 views

0 replies

Started 2 months ago
by alinx
Not Answered
How to use duel core for cycloneVsoc board by baremetal 0
193 views

0 replies

Started 2 months ago
by Chun Alex
Answered

AXI narrow burst support +1

1076 views

8 replies

Latest 2 months ago
by deepakmathew