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Enabling MPU causes clearing of Stack in Cortex R5F


After enabling MPU, my stack is getting cleared. 

If the caches are disabled, it works fine. But when the caches are enabled, this problem occurs.

what is the relation between MPU and Cache in this context ?

Can anyone please explain. 


  • I suspect the answer is to do with changing of cache-ability.

    When the MPU on the Cortex-R5 is disabled, a "default" set of MPU regions are used. These are described here:

    So, if you run with the MPU disabled and data cache enabled, some data accesses could result in lines being pulled into the data cache.  And, if the region is write-back, then writes might only be initially done into to the data cache. If you then enable the MPU, the Cortex-R5 will start using whatever properties you've now specified in the regions. If a given address goes from cacheable to non-cacheable, that could lead you no longer "seeing" data previous pulled into the data cache.