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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Suggested Answer

    Armv7-M and Cortex-M3 0

    • Armv7-M
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    2627 views
    1 reply
    Latest over 2 years ago
    by Siyu Mou Arm Employee Badge
  • Not Answered

    What is the need of EMPTY state of cache in the CHI protocol 0

    845 views
    0 replies
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  • Not Answered

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    1195 views
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    1606 views
    3 replies
    Latest over 2 years ago
    by purna chandu
  • Not Answered

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    • Armv7 Exception Model
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    • Cortex-M
    1127 views
    1 reply
    Latest over 2 years ago
    by Sherry Zhang Arm Employee Badge
  • Not Answered

    short term clock stop 0

    805 views
    0 replies
    Started over 2 years ago
    by aaron_aaron
  • Suggested Answer

    Query suggestions on GIC registers accessing latency 0

    1049 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    PMU event count register PMEVCNTR<n> alway is 0 +1

    • Real Time Operating Systems (RTOS)
    • Cortex-A72
    • 12 (Debug Monitor)
    • performance analysis
    • Armv8-A
    • Debug and Analysis
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    Latest over 2 years ago
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  • Not Answered

    ARM A76 watchpoint does not work 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A76
    • threadx
    • Debug and Trace
    855 views
    0 replies
    Started over 2 years ago
    by PMU_study
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    Understanding of cortex-a8 neon pipeline 0

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    by Ramesh Nagapuri
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    1285 views
    0 replies
    Started over 2 years ago
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  • Answered

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    • Registers
    • Cortex-M3
    2364 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Initialization of PL310 RAM arrays 0

    • Cache Controllers
    747 views
    0 replies
    Started over 2 years ago
    by Wenchien
  • Answered

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    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    • Generic Interrupt Controller
    • CoreLink GIC-600AE
    1650 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Is there an IntMemAxi for 128-bit memories? 0

    • Cortex-R52
    • AXI4
    • SRAM
    834 views
    0 replies
    Started over 2 years ago
    by tjones95134
  • Answered

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    • GICv2
    • GICv3/v4
    3026 views
    2 replies
    Latest over 2 years ago
    by Jorge
  • Answered

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    • GICv3/v4
    • Cortex-A55
    • Armv8-A
    3261 views
    3 replies
    Latest over 2 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    DAIF related instructions/operations are very expensive on Cortex-A72(Armv8.0) compared to Cortex-A53. 0

    1827 views
    1 reply
    Latest over 2 years ago
    by Coarestligh
  • Not Answered

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    • CPU Architecture
    • virtualization
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    1 reply
    Latest over 2 years ago
    by Frank Wiles
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    945 views
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