Hi all,
We have a CPU subsystem which we are independently simulating using a hardware simulator (VCS) and mapping onto a Xilinx FPGA with a Keil ULink2 and ARM DS attached. It is based on a Cortex-M7, r1p2-00rel0.
The simulations complete discovery just fine.The DS discovery on the FPGA mapping correctly decodes a system ROM table sitting on the APB network behind a JTAG Debug Port. It then correctly decodes the Cortex-M7 Processor ROM table via an AHB Access Port.The first entry of that Processor ROM table points to the PPB ROM table based at 0xE00F_F000 and so DS goes off to read that but comes back with:
[30/08/23 13:05:31] Valid ROM table entries are:
[30/08/23 13:05:31] 0x00001003 (component base address: 0xE00FF000)
[30/08/23 13:05:31] 0xFFF43003 (component base address: 0xE0041000)
[30/08/23 13:05:31] 0xFFF44003 (component base address: 0xE0042000)
[30/08/23 13:05:31] 0x1FF02002 (component base address: 0x00000000 - Entry Present bit not set, no device interrogation will occur.)
[30/08/23 13:05:31] Reading peripheral and component ID registers of device at address 0xE00FF000
[30/08/23 13:05:31] Failed to process component at address 0xE00FF000 from ROM table at address 0xE00FE000: Failed to read 16 bytes from address 0xE00FFFF0 on CSMEMAP_0
[30/08/23 13:05:31] Reading peripheral and component ID registers of device at address 0xE0041000
[30/08/23 13:05:31] Failed to process component at address 0xE0041000 from ROM table at address 0xE00FE000: Failed to read 16 bytes from address 0xE0041FF0 on CSMEMAP_0
[30/08/23 13:05:31] Reading peripheral and component ID registers of device at address 0xE0042000
[30/08/23 13:05:31] Failed to process component at address 0xE0042000 from ROM table at address 0xE00FE000: Failed to read 16 bytes from address 0xE0042FF0 on CSMEMAP_0
[30/08/23 13:05:31] End of ROM table
[30/08/23 13:05:31] Could not detect embedded APs: Unable to connect to device CSMEMAP_1
What is particularly strange is that, when I look at what the CXDT testbench is doing in simulation, the point at which I see the CIDs of the PPB ROM table being read, the addresses on the transactions between the Coresight AHB-AP and the CM-7 AHBD are all 0xE000EF** and NOT 0xE00FFF**Can anyone explain the relationship between the two address in the sentece above? - the former seems to fit neither with the CSMEMAP_0 nor CSMEMAP_1 regioning.And, ultimately, given that all the M7 clocks look to be running on the FPGA, can anyone think of any reason why the PPB ROM reads should fail in DS when the Processor ROM was read just fine? Is there a dependency on something else - a pin being set a particular way, reset deassertion ordering, etc...? Or could there be a failed attempt for a transaction to go back out on the EPPB during this stage of discovery?Many thanks