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CYCLONE V - HPS - DDR RAM CONTROL OVER JTAG WITH OPENOCD

Hello,

I am trying to access a PCB with Cyclone V using JTAG.

I am using OpenOCD for this purpose, and I am making the JTAG connection to the HPS side of Cyclone V.

You can find the OpenOCD configuration file I used below.

First, I run OpenOCD from the command line. Then, I connect to the OpenOCD server using the "telnet 127.0.0.1 4444" command. I halt the processor using the "halt" command, and so far, there are no issues.

However, when I try to access the SDRAM blocks, it gives an error. For example, when I execute the "mdw 0x00000000" command, I can read successfully, but when I execute the "mdw 0x00010000" command, it gives an error.

Actually, my goal is to access the HPS through JTAG and control the SDRAM Controller Subsystem to read from and write data to DDR RAM. Is there anything I'm missing or doing wrong in this process?

Thanks.

My config file:

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#
# Altera cyclone V SoC family, 5Cxxx
#
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME fpgasoc
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#
# Altera cyclone V SoC family, 5Cxxx
#
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME fpgasoc
}

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID




#
# Cortex-A9 target
#

# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0  -  0x80110000
# core 1  -  0x80112000

# Slow speed to be sure it will work
adapter_khz 1000

set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1

# A9 core 0
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
        -coreid 0 -dbgbase 0x80110000

$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
$_TARGETNAME1 configure -event gdb-attach { halt }


# A9 core 1
#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
#        -coreid 1 -dbgbase 0x80112000

#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
#$_TARGETNAME2 configure -event gdb-attach { halt }

proc cycv_dbginit {target} {
        # General Cortex-A8/A9 debug initialisation
        cortex_a dbginit
}