Hi expert,
After enabling TZC, both bus error and interrupt occur if the transaction is illegal. The software only processes the bus error by Synchronous(vector table), not entering the interrupt handle. And the system will get stuck
From TZC:
DDI0504C_tzc400_r0p1_trm.pdf
Set If an ACE-Lite transaction has insufficient security privileges, then for: decode error and raise an interrupt
This enables the issuing master to behave as though the memory location is absent. The TZC-400 presents a DECERR response and generates an interrupt
sync handler:
.section DefaultHandleEL3, "ax" .balign 4 .type default_handle_el3, "function" default_handle_el3: msr spsel, #0 STP x29, x30, [sp, #-16]! STP x18, x19, [sp, #-16]! STP x16, x17, [sp, #-16]! STP x14, x15, [sp, #-16]! STP x12, x13, [sp, #-16]! STP x10, x11, [sp, #-16]! STP x8, x9, [sp, #-16]! STP x6, x7, [sp, #-16]! STP x4, x5, [sp, #-16]! STP x2, x3, [sp, #-16]! STP x0, x1, [sp, #-16]! mrs x0, elr_el3 add x0, x0, #4 msr elr_el3, x0 BL synchandler LDP x0, x1, [sp], #16 LDP x2, x3, [sp], #16 LDP x4, x5, [sp], #16 LDP x6, x7, [sp], #16 LDP x8, x9, [sp], #16 LDP x10, x11, [sp], #16 LDP x12, x13, [sp], #16 LDP x14, x15, [sp], #16 LDP x16, x17, [sp], #16 LDP x18, x19, [sp], #16 LDP x29, x30, [sp], #16 ERET
IRQ handler:
.section InterruptHandlers, "ax" .balign 4 .type irq_handle_el3, "function" irq_handle_el3: msr spsel, #0 STP x29, x30, [sp, #-16]! STP x18, x19, [sp, #-16]! STP x16, x17, [sp, #-16]! STP x14, x15, [sp, #-16]! STP x12, x13, [sp, #-16]! STP x10, x11, [sp, #-16]! STP x8, x9, [sp, #-16]! STP x6, x7, [sp, #-16]! STP x4, x5, [sp, #-16]! STP x2, x3, [sp, #-16]! STP x0, x1, [sp, #-16]! BL sys_irq LDP x0, x1, [sp], #16 LDP x2, x3, [sp], #16 LDP x4, x5, [sp], #16 LDP x6, x7, [sp], #16 LDP x8, x9, [sp], #16 LDP x10, x11, [sp], #16 LDP x12, x13, [sp], #16 LDP x14, x15, [sp], #16 LDP x16, x17, [sp], #16 LDP x18, x19, [sp], #16 LDP x29, x30, [sp], #16 ERET
Thanks.