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SMMUv2 IRQS per Context Bank

SMMUv2 spec explicitely says there must be an IRQ per Context Bank.

- #global-interrupts : The number of global interrupts exposed by the

- interrupts    : Interrupt list, with the first #global-irqs entries
                  corresponding to the global interrupts and any
                  following entries corresponding to context interrupts,
                  specified in order of their indexing by the SMMU.

                  For SMMUv2 implementations, there must be exactly one
                  interrupt per context bank. In the case of a single,
                  combined interrupt, it must be listed multiple times.

When looking at Nvidia-jetson Orin dts, we see there are several context banks with a single combined interrupt.

0x00 0xaa 0x04 - The SPI (0xaa + 32) is a single-combined interrupt.

My question is, when the SPI is generated, what is the most efficient way  for the software to know which context bank asserted it?

Thanks in advance