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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3588 Questions
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  • Not Answered

    A53 Asynchronous Multi-Processing questions 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A53
    • Multiprocessor Architecture
    • Real-Time
    • Asynchronous Operation
    • Baremetal
    1164 views
    0 replies
    Started over 2 years ago
    by PeppeAv
  • Not Answered

    Will an outer non-cachable-write invalidate cacheline when hit in l2cache, with shared override bit set 0

    773 views
    0 replies
    Started over 2 years ago
    by shch
  • Not Answered

    Coremark value for the Cortex A78-AE processor? 0

    1508 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Answered

    Cortex M3 goes into osRtxIdleThread when jumping to __main 0

    • Cortex-M3
    • Cortex-M
    1368 views
    2 replies
    Latest over 2 years ago
    by Arran
  • Answered

    Armv8-2 Error Injection Registers 0

    • Armv8-A
    1900 views
    3 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    FVP peripheral supports 0

    • SMMUv3
    • Fixed Virtual Platforms (FVPs)
    1268 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    When GICD_IERRR bit set ? 0

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    • CoreLink GIC-600AE
    1634 views
    3 replies
    Latest over 2 years ago
    by Namu
  • Answered

    About CPU behavior when it receives error response signal during reading or writing 0

    1599 views
    2 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Understanding ARM core performance 0

    1260 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Not Answered

    Understanding ARM core performance 0

    598 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Suggested Answer

    Cortex A55 : Hotplug of secondary core 0

    • Cortex-A55
    • Armv8-A
    • Cortex-A
    2684 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    How peripherals are accessible between NW and SW? 0

    • SMMUv3
    • Peripheral Controllers
    • TrustZone
    1082 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    What does "Bit-Band Operation of Different Data sizes" meaning? 0

    • Cortex-M
    815 views
    0 replies
    Started over 2 years ago
    by shadow3d
  • Answered

    Does NIC-400/AXI provide full theoretical bandwidth 0

    • CoreLink NIC-400
    • AXI4
    1311 views
    1 reply
    Latest over 2 years ago
    by Ryleigh Sawayn
  • Not Answered

    What A53 interrupt signal should I use for watchdog timeout? 0

    • Cortex-A53
    1361 views
    1 reply
    Latest over 2 years ago
    by Ryleigh Sawayn
  • Answered

    Migration from Cortex M4 to Cortex R5F 0

    • Software
    • Cortex-R5
    • Cortex-M4
    2861 views
    3 replies
    Latest over 2 years ago
    by Ryleigh Sawayn
  • Not Answered

    Cortex-A53 PMU: Read Allocate Mode Event Definition (BUS_ACCESS erratum work-around) 0

    • Cortex-A53
    1208 views
    0 replies
    Started over 2 years ago
    by rayman_de
  • Not Answered

    pl330 scatter-gather transfer 0

    1337 views
    2 replies
    Latest over 2 years ago
    by GuillaumeB
  • Answered

    Reading Cortex-A9 CNTFRQ register using ARM Compiler 5 inline assembly 0

    • Cortex-A9
    • Arm Assembly Language (ASM)
    • Arm Compiler 5
    3175 views
    7 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Cortex-A9 , get CPU frequency , bare metal 0

    • Cortex-A9
    • Baremetal
    2270 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
<>
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