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ARM64 - Simple EL2 MMU Configuration

I am doing an MMU experiment with Raspberry Pi 3B (Quad core Cortex A53) board. The board starts in EL2. From EL2, the stage-2 MMU is configured. It is configured to have a one-to-one mapping (that is Intermediate Physical Address and Physical Address are same). The code in EL2 is continuing to execute after the MMU is enabled (HCR_EL2.VM=1). But when the code switches to EL1 (After ERET instruction), the memory contains random data. If I inspect the memory before ERET, using a debugger, it contains valid code. May I know the reason for this?

The page table configuration uses 64KB granule. The Level-2 table entries points to 512MB blocks. For reference, the important steps of my configuration is given below. Any hint is greatly appreciated.

ldr x1, =tt_s2_l1_base  
msr vttbr_el2, x1  

movz x0, 0x755c
movk x0, 0x0001, lsl 16  //64KB granule, 512MB block
msr vtcr_el2, x0

ldr x1, =tt_s2_l1_base  // Address of L1 table
movz x0,0x0000
orr x0, x0, 0x01
orr x0, x0, 0xc0
orr x0, x0, 0x400
orr x0, x0, 0x300
str x0, [x1] //first page table entry configuration

dsb SY

msr  sctlr_el1, xzr

tlbi  VMALLE1
dsb  SY

mrs x0, hcr_el2 
orr x0, x0, #0x1 //enable stage-2 address translation
orr x0, x0, #(1<<31)   // RW=1 EL1 Execution state is AArch64.
msr hcr_el2, x0

movz x2, 0x03c5 //DAIF masked
movk x2, 0x0000, lsl #16 
msr     spsr_el2, x2 //Saved program status register

movz x0, 0x0000
movk x0, 0x100, lsl #16
msr elr_el2, x0 

dsb  SY