According to https://developer.arm.com/documentation/102379/0101/The-processor-timers?lang=en
The interrupts generated by the timer behave in a level-sensitive manner. This means that, once the timer firing condition is reached, the timer will continue to signal an interrupt until one of the following situations occurs:
When writing an interrupt handler for the timers, it is important that software clears the interrupt before deactivating the interrupt in the GIC. Otherwise the GIC will re-signal the same interrupt again."Does it mean we need a synchronization barrier (e.g. isb()) between two points:P1. TVAL gets updated. The firing confition is no longer met.
P2. ICC_EOIR, ICC_DIROr ISB() is not enough and we need something else there?Thanks in advance
The ISB ensures that the effects of the write to TVAL is visible to the ICC_EOIR/ICC_DIR. So yes, without you increase the chance of the timer interrupt signal still being asserted to the GIC when the Deactivate is sent if you remove the ISB.