I'm trying to bare-metal debug on a Cortex-M3.I want to perform simple memory read/write, but the address is translated unintentionally. How can I stop address conversion?
Specifically, although I want to access address 0x22800000, it accesses address 0x20040000. If you read the disassembled code, it looks like you are accessing address 0x22800000.*Because 0x22800000 is set in the general-purpose registerDisplaying Memory View at address 0x22800000 with DS-5 will show the memory status at address 0x20040000.
The MPU settings are as follows. Disabling SCS.MPU.Ctrl does not change the phenomenon.
SCS.MPU.RegionBaseAddr = ((unsigned int) 0x20000000) | REGION_VALID | 5; SCS.MPU.RegionAttrSize = FULL_ACCESS | CACHEABLE | BUFFERABLE | REGION_512M | REGION_ENABLED; SCS.MPU.Ctrl |= 1;"
It seems your device has implemented bit-banding:https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/memory-model/optional-bit-banding
Which exact device are you using?
Thank you for your reply.
Certainly, I also felt that bit-banding was implemented.
Since the target board is a virtual prototype, the development environment is completed on the PC. Siemens VISTA is used as the virtual prototype development tool.Therefore, the device (model) uses the VISTA library. When generating the model, the option setting item was only the amount of IRQ, so bit-banding was not implemented intentionally.
By the way, does the presence or absence of the bit-banding function depend on the implementation (the device or model being used)? If it depends and is implemented, is there a way to avoid it by changing the settings?
Yes, it is a parameter set in RTL. It should be described in the integration manual.
I couldn't find the manual for Cortex-M3 in the VISTA library, so I looked at the Cortex-M7 manual, but there was no such parameter.* For example, if there was a parameter like the following. NUM_IRQ HAS_EXTERNAL_ITCM icache_size fpu_type mpu_number_regions CPUID
Do you know the parameter name? When I referred to the integration manual for ASIC, I found a parameter called BB_PRESENT.Are you talking about this?
* I checked what BB_PRESENT indicates by referring to the manual below, but I didn't understand. Arm®v7-M Architecture Reference Manual Cortex -M3 Technical Reference Manual Cortex -M3 Devices Generic User Guide
* BB_PRESENT is set to 0 according to the ASIC's integration manual. The memory map I'm trying to build on VISTA's Cortex-M3 model is optimized for this ASIC.
If I know the parameter name for implementing bit-banding, I will ask VISTA's inquiry desk about the setting method in the Cortex-M3 model.
I would guess that `BB_PRESENT` is the correct parameter, but I do not know for certain (IP integration is not my area of expertise!).
Suggest you raise an official support request from the support menu above. This seems to be beyond the scope of public forum support.
I got it. Regarding the parameter name, I would like to inquire from the support menu.
When I checked the address conversion formula, it matched the bit-banding specification, so it seems that there is no doubt that this function is implemented.
I would like to close this issue. Thank you for your guidance.