Hi,
We discovered that some special register operations are very expensive on Cortex-A72(Armv8.0) compared to Cortex-A53. Is there any way to narrow the gap? Thanks.
Results as below,Operation cost (ns)Operation Cortex-A72(1.8GHz) Cortex-A53(1.6GHz)unconditionally disable interrupts 20 0.63unconditionally enable interrupts 20 0.63read flags 9.5 0.63write flags 20 5.60
Some details:Unconditionally disable interrupts is: “msr daifset, #3”.Unconditionally enable interrupts is: “msr daifclr, #3”.Read flags is: “mrs reg, daif”.Write flags is “msr daif, reg”.
Hello,The differences you are observing in the cost of special register operations between Cortex-A72 and Cortex-A53 are expected due to the architectural differences between these processors. Cortex-A72 is a higher-performance core designed for more demanding workloads, while Cortex-A53 is a more power-efficient core.
To narrow the gap in the cost of these operations, you can consider the following suggestions:
Optimize Interrupt Handling: Review your code and interrupt handling mechanisms to minimize the frequency and duration of interrupt operations. Efficient interrupt handling can help reduce the impact of the expensive interrupt-related register operations.Utilize Conditional Register Operations: Instead of unconditionally enabling or disabling interrupts, consider using conditional register operations where possible. This approach allows you to selectively enable or disable interrupts based on specific conditions, reducing the need for expensive unconditional operations.Limit Flag Register Access: Minimize the frequency of reading and writing flags by carefully analyzing your code and ensuring that flag register access is only performed when necessary. Avoid unnecessary flag manipulation that can add overhead to your operations. PaybyPlateMaEvaluate Compiler Optimization: Make sure you are using the latest version of the compiler and enable appropriate optimization flags to take advantage of any architecture-specific optimizations. Compiler optimizations can sometimes help in reducing the cost of register operations.Consider Targeting Cortex-A72 Specifically: If your application predominantly runs on Cortex-A72, you can consider tailoring your code and algorithms specifically for this core. By leveraging the specific features and performance characteristics of Cortex-A72, you may be able to optimize your code further.
It's important to note that the cost of these register operations can vary depending on the specific microarchitecture and implementation details. Therefore, it's recommended to consult the ARM Architecture Reference Manual and the documentation specific to your Cortex-A72 and Cortex-A53 implementations for detailed information on register operations and optimization techniques.
Best regard,Coarestligh