Is there any use case where this register (ICH_EISR_EL2) can report more than one outstanding EOI?I don't really understand why we have 16-bit wide register (one bit per LR) if there is no use-case. I'm sure I'm missing something.
(i) It seems in terms of HW implementation this feature could be implemented by having some combinational logic between LRs and the bits of EISR.EISR_Bit 0 = (LR.Inactive is true) & (LR.HW is false) & (LR.EOI is true);This would make the update of the register nearly immediately with some combinational logic.(ii) Now I'm looking for a case by each ICV_EOI/DIR propagation to update the ICH_LR takes longer than handling a next IRQ. When the maintenance IRQ is generated there will be 2 EOId vIRQs set in the LRs and not 1.(iii) Next, lets assume, the EISR bit gets true nearly immediately, the LR.Status update very fast as well. Is it possible for an implementation to have a certain timeout on the maintenance IRQ that would give the vCPU time to handle more than vIRQ (LR.EOI=1) before getting the maintenance IRQ?@Martin Weidmann need your expertise here.
Sharing some experiments:
do { u32 irqstat = gic_read_iar(); u32 irqnr = gic_iar_irqnr(irqstat); if (irqnr != GICC_INT_SPURIOUS) { ... delay ... gic_write_eoir(irqstat); } else { break; } } while (1);
do { u32 irqstat = gic_read_iar(); u32 irqnr = gic_iar_irqnr(irqstat); if (irqnr != GICC_INT_SPURIOUS) { < IRQ Handling > gic_write_eoir(irqstat); } else { break; } } while (1); MSR(ICC_DIR_EL1, 7); MSR(ICC_DIR_EL1, 6); MSR(ICC_DIR_EL1, 5); MSR(ICC_DIR_EL1, 4);