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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Not Answered

    Multi-layer AHB-Lite - Handling of HREADY for back-to-back transfers from different managers +1

    1771 views
    0 replies
    Started over 2 years ago
    by SvenCo
  • Answered

    FastModel with CMN700 +1

    • NI-700
    • AArch64
    • Fast Models
    • Neoverse N1
    • corelink cmn-600
    2924 views
    2 replies
    Latest over 2 years ago
    by klka
  • Suggested Answer

    Are there performance indicators for bridges? 0

    • Bridges Interfaces and Modules
    • AMBA
    • Bus Interface
    • SoC FPGA
    1875 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    AHB error response to two pipelined non-burst transactions 0

    • AHB
    4121 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    In CHI spec, if the Requester initial state is UD or SD, what the final cache state of a ReadClean transaction should be? +1

    2612 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    CHI problem 0

    2031 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    AXI3: Out of order write transaction 0

    4172 views
    4 replies
    Latest over 2 years ago
    by alan.k.yang
  • Suggested Answer

    About the PrimeCell®︎ DMA Controller (PL080) internal FIFOs. 0

    • PrimeCell DMA Controller (PL080)
    3545 views
    5 replies
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    How to download M55r1p1 0

    1772 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Emulation friendly CoreSight debug platform 0

    2252 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Area growth characteristics of SMIC28 memory such as DPRAM, Two PORT ram, spram and ROM. 0

    • 28 nm
    • ROM Memory
    • SRAM Memory
    • dram
    1751 views
    1 reply
    Latest over 2 years ago
    by Stephen Theobald Arm Employee Badge
  • Suggested Answer

    Instable Coresight Unit in DesignStart FPGA Cortex M0 0

    • Keil
    • DesignStart
    • Debugging
    • Arm V2C-DAP Link for DesignStart FPGA
    3387 views
    4 replies
    Latest over 3 years ago
    by rainier
  • Not Answered

    UMC28nm process library unit 0

    1550 views
    1 reply
    Latest over 3 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    AMBA bus Spec 0

    • AMBA 4
    • AXI4
    3204 views
    2 replies
    Latest over 3 years ago
    by James Bradley
  • Answered

    Question regarding IP-XACT Bus Definition of AMBA5 AHB5Initiator +1

    3261 views
    3 replies
    Latest over 3 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    How to merge two PC traces of ARM Cortex M7 0

    1950 views
    2 replies
    Latest over 3 years ago
    by moh30
  • Suggested Answer

    How to license modeldebugger included in free Base_RevC_AEMvA_pkg? 0

    • AEMv8 FVP
    3746 views
    5 replies
    Latest over 3 years ago
    by ibkev
  • Not Answered

    Can I keep TKEEP as a constant in a MMU? 0

    1054 views
    0 replies
    Started over 3 years ago
    by Lidoon
  • Answered

    Armv8-R AEM FVP trap to EL2 missing information in HSR on guest's STRD 0

    • AEMv8 FVP
    • Armv8-R
    • Hypervisor
    • AArch32
    7863 views
    13 replies
    Latest over 3 years ago
    by weichen Arm Employee Badge
  • Suggested Answer

    cpu sim 0

    5922 views
    8 replies
    Latest over 3 years ago
    by Toshihisa Oishi Arm Employee Badge
<>
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