Multi-layer AHB-Lite - Handling of HREADY for back-to-back transfers from different managers

Dear ARM community,

I'm implementing a multi-layer AHB-Lite system based on dvi0045 and have some doubts about the handling of HREADY.

TL;DR: Is it possible to interleave transfers of different AHB-Lite managers, if a multi-layer AHB-Lite interconnect matrix is used? What is the expected behavior seen on the subordinate interface HREADY signal, if transfers of different manager are issued back-to-back?

Consider the following system: Two AHB-Lite managers, let us call them M1 and M2, and two AHB-Lite subordinates S1 and S2 are connected to a multi-layer AHB-Lite interconnect matrix. Arbitration follows a simple priority scheme. M1 is the default manager and has priority over M2. Arbitration shall be handled in a single cycle, i.e. no wait state shall be inserted by the interconnect matrix for arbitration, unless the newly selected subordinate is already handling an active request from another manager.

The following scenario is applied to the system:

  • Cycle 1
    • M1: Drives control signals for access to S1
    • M2: Drives control signals for access to S2
    • S1: Selected for NONSEQ access from S1
    • S2: Selected for NONSEQ access from S2
  • Cycle 2
    • M1: Drives control signals for access to S2
    • M2: Drives IDLE
    • S1: Stalls the response to M1, no longer selected for further transfers.
    • S2: Drives response to M2. Selected for NONSEQ access from S1, but has to wait for HREADY from S1 to rise.
  • Cycle 3
    • M1: Holds control signals for access to S2
    • M2: Drives IDLE
    • S1: Drives response to M1. Raises HREADY.
    • S2: Selected for NONSEQ access from S1.
  • Cycle 4
    • M1; Drives IDLE
    • M2: Drives IDLE
    • S1: Don't care
    • S2: Drives response to M1.

See also the following abstract waveform: /resized-image/__size/640x480/__key/communityserver-discussions-components-files/476/ml_5F00_ahb_2D00_lite_5F00_hready_5F00_ex.png

The point I'm not sure about is the forwarding of M1 HREADY to S2, while S2 is in the M1 access data phase. Marked in bold above. During verification no data consistency issue is observed for any subordinate or manager. Still, a protocol check fires in cycle 2, because S2 HREADY is not expected to be low, since S2 itself is not driving HREADYOUT low.

From my point of view the observed behavior is fine in multi-layer AHB-Lite for the following reasons:

  1. As per my understanding of the AMBA5 AHB-Lite specification the HREADY of any manager, and thereby of any subordinate selected by that manager, has to follow the HREADYOU of the subordinate currently in data phase to said manager. So, if our arbiter switches managers, the HREADY of the newly selected manager will also be applied. (see also KA001342) Otherwise bus collisions could occur.
  2. In the example above, if M1 would not access S2, M1 would still broadcast all control signals to S2, because M1 is the default manager. The only difference would be that HSEL is low for S2, it would still see the difference between HREADY and HREADYOUT.

But there are also conflicting resources, indicating that from a subordinate perspective HREADY always has to mirror HREADYOUT while it is in an active data phase. For example,

Happy to hear your thoughts and thank you for your time.