Dear ARM community,
I'm implementing a multi-layer AHB-Lite system based on dvi0045 and have some doubts about the handling of HREADY.
TL;DR: Is it possible to interleave transfers of different AHB-Lite managers, if a multi-layer AHB-Lite interconnect matrix is used? What is the expected behavior seen on the subordinate interface HREADY signal, if transfers of different manager are issued back-to-back?
Consider the following system: Two AHB-Lite managers, let us call them M1 and M2, and two AHB-Lite subordinates S1 and S2 are connected to a multi-layer AHB-Lite interconnect matrix. Arbitration follows a simple priority scheme. M1 is the default manager and has priority over M2. Arbitration shall be handled in a single cycle, i.e. no wait state shall be inserted by the interconnect matrix for arbitration, unless the newly selected subordinate is already handling an active request from another manager.
The following scenario is applied to the system:
See also the following abstract waveform: /resized-image/__size/640x480/__key/communityserver-discussions-components-files/476/ml_5F00_ahb_2D00_lite_5F00_hready_5F00_ex.png
The point I'm not sure about is the forwarding of M1 HREADY to S2, while S2 is in the M1 access data phase. Marked in bold above. During verification no data consistency issue is observed for any subordinate or manager. Still, a protocol check fires in cycle 2, because S2 HREADY is not expected to be low, since S2 itself is not driving HREADYOUT low.
From my point of view the observed behavior is fine in multi-layer AHB-Lite for the following reasons:
But there are also conflicting resources, indicating that from a subordinate perspective HREADY always has to mirror HREADYOUT while it is in an active data phase. For example, https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000007MoXOUA0&pageName=ArticleContent.
Happy to hear your thoughts and thank you for your time.