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Armv8-R AEM FVP AArch32 mode - Access to IMP_CBAR causes a crash

Refer Cortex R52 TRM, 3.3.17  "Configuration Base Address Register"

"The IMP_CBAR holds the physical base address of the memory-mapped GIC Distributor registers."

However when I try to access this register, it causes a trap as "Undefined instruction".

Can you help me here ?

  • executed is not recognized by the processor. This could be due to a number of reasons, including incorrect configuration of the memory-mapped GIC Distributor registers, incorrect access permissions for the process attempting to access the register, or the instruction being unsupported on the specific processor.

    In order to resolve this issue, you may want to verify that the memory-mapped GIC Distributor register has been configured correctly and that the process attempting to access the register has the correct access permissions. Additionally, you may want to check the specifications of the Cortex R52 processor you are using to ensure that it supports the instruction being executed.

  • Hi Ayan - AEM FVP is not a core specific model so it doesn't have implementation defined registers such as IMP_CBAR. Please use ARMCortexR52x1CT (see the link below), instead.

    It's a license protected FVP. If you'd like to purchase or evaluate the FVP, please contact Arm representatives.