APB control signals behavior before psel is asserted

In APB spec all the control/addr signals are changing exactly when psel is enabled, but I have seen designs where pwrite/paddr/pwdata data asserted before psel=1. This implementation seems to be fine, but is this valid behavior as  per protocol? 

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  • The PWRITE/PADDR/PWDATA signals do not have any "default" value, so are undefined outside of a transfer. So they could change outside of when APB transfers are being performed.

    The APB protocol diagrams will show these signals changing when an APB transfer starts as that is when the APB initiator would ensure all its outputs would be valid for the transfer to be performed, and from a power perspective you probably don't want these control signals toggling randomly outside transfers, so that is why you see the nice "clean" behaviour in the APB spec diagrams.

    However there wouldn't be anything wrong with the APB initiator driving these control signals valid maybe a cycle or two before a transfer is started, but this isn't required by the protocol.

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  • The PWRITE/PADDR/PWDATA signals do not have any "default" value, so are undefined outside of a transfer. So they could change outside of when APB transfers are being performed.

    The APB protocol diagrams will show these signals changing when an APB transfer starts as that is when the APB initiator would ensure all its outputs would be valid for the transfer to be performed, and from a power perspective you probably don't want these control signals toggling randomly outside transfers, so that is why you see the nice "clean" behaviour in the APB spec diagrams.

    However there wouldn't be anything wrong with the APB initiator driving these control signals valid maybe a cycle or two before a transfer is started, but this isn't required by the protocol.

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