Refer Cortex R52 TRM, 3.3.17 "Configuration Base Address Register"
"The IMP_CBAR holds the physical base address of the memory-mapped GIC Distributor registers."
However when I try to access this register, it causes a trap as "Undefined instruction".
Can you help me here ?
Hi Ayan - AEM FVP is not a core specific model so it doesn't have implementation defined registers such as IMP_CBAR. Please use ARMCortexR52x1CT (see the link below), instead.
It's a license protected FVP. If you'd like to purchase or evaluate the FVP, please contact Arm representatives.