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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 739 Questions
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  • Answered

    Wondering about PPROT[2] 0

    • APB
    • AMBA
    3850 views
    2 replies
    Latest over 2 years ago
    by Mr.KIM
  • Not Answered

    Trying to locate UMC 22nm USK DSK supplemental library or alternative. 0

    1075 views
    0 replies
    Started over 2 years ago
    by Former Member
  • Suggested Answer

    Question about amba ahb5 wait states 0

    • AHB
    2065 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    How does QoS work with priority and ordering? 0

    • AMBA 3 AXI Interface
    • AXI4
    3445 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Cache State wrt ReadShared and ReadOnce 0

    • Cache coherency
    • ACE
    2253 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    How does BP131 Downsizer addressing work? 0

    • PrimeCell BP131
    1934 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    method to test cache on chip 0

    • Cortex-A53
    • System on Chip (SoC)
    • SoC Verification
    1037 views
    0 replies
    Started over 2 years ago
    by WatterCutter
  • Answered

    CHI-B Interface user sideband 0

    • AMBA 5 CHI
    2238 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    To PIL or not to PIL 0

    1167 views
    0 replies
    Started over 2 years ago
    by tjones95134
  • Not Answered

    fault_s signal holds unknown value at power-up 0

    • Cortex-R5
    1054 views
    0 replies
    Started over 2 years ago
    by ele
  • Answered

    1kB boundary concept in AHB 0

    5005 views
    2 replies
    Latest over 2 years ago
    by Almailtu
  • Not Answered

    AMBA Low power interface relation with QACTIVE, QDENY and PWAKEUP 0

    • AMBA
    3511 views
    3 replies
    Latest over 2 years ago
    by Annie
  • Not Answered

    Regarding Strobe IN AXI4 0

    • AXI4
    2334 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Does APB allow multiple beats in a transfer like AXI/AHB? 0

    3191 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    The reason why AHB Slave has HREADY input and output both 0

    • AMBA 3 AHB Interface
    • AHB-Lite
    • AMBA 2 AHB Interface
    • AHB
    8949 views
    3 replies
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    single clock edge operation in AMBA AHB? 0

    • AMBA
    • AMBA 2
    • AHB
    3010 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    scenario for PO&POE on ARM Artiasn GPIO ? 0

    1546 views
    0 replies
    Started over 2 years ago
    by yfb
  • Not Answered

    the scenarios for fail-safe ,retention and core down on GPIO? 0

    1497 views
    0 replies
    Started over 2 years ago
    by yfb
  • Not Answered

    NIC400 Axi4 Limit total number of outstanding transactions to 1 0

    • AXI4
    1149 views
    0 replies
    Started over 2 years ago
    by hasansatana
  • Not Answered

    The cyclone v soc GIC interrupt priority issues 0

    • GIC-390 PrimeCell PL390
    • Cortex-A
    1209 views
    0 replies
    Started over 2 years ago
    by Chun Alex
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