Trying to understand About the AXI downsizer.
There are explaining especially two mode.
3.1 Pass-through modeWhen the size of an incoming transaction is 32 bits or less, DownsizerAxi operates inpass-through mode. In pass-through mode, the first data transfer of the transaction cantake place two clock cycles after AxVALIDS is asserted. When a transaction is inprogress, the input and output data channels are connected by combinatorial logic anddata transfer continues at one data transfer per clock cycle.
3.2 Downsize modeWhen the size of an incoming transaction is 64 bits, DownsizerAxi operates in downsizemode. In downsize mode, DownsizerAxi converts the incoming 64-bit transaction intoone or more 32-bit transactions. The number of 32-bit transactions that DownsizerAxigenerates depends on the burst type, AxBURST, and length, AxLEN, of the 64-bittransaction.The first 32-bit data transfer of the transaction can take place two clock cycles afterAxVALIDS is asserted. The first 64-bit transfer can complete three clock cycles afterAxVALIDS is asserted. The extra clock cycle is required because the 64-bit datatransfer is made up of two 32-bit data transfers.
Let's say I want to write 64bit transaction to 32bit by downsizer, address: 0x8000_0000 and wdata: 0x1234_5678_abcd_feed. Probably it will write in Downsize mode.
but In especially, I'm confused that address processing at that time. when it writes two 32bit data, how does the address process?
address: 0x8000_0000 and wdata: 0x1234_5678.
address: 0x8000_0000 and wdata: 0xabcd_feed.
1. address: 0x8000_0000 and wdata: 0x1234_5678.
2. address: 0x8000_0004 and wdata: 0xabcd_feed.
How does address correctly work?
As AXI transactions can contain multiple data transfers, a downsizing component would just convert a single 64-bit write into two 32-bit writes, so a 1-beat transaction becoming a 2-beat transaction.
This generated 2-beat transaction would just have the one AW address transfer (the 0x8000_0000 in your example), with WDATA transfers of 0xabcd_feed and then 0x1234_5678.
If the original 64-bit transaction has 2 or more data transfers, the burst type (FIXED/INCR/WRAP) and original burst length will determine whether longer transaction lengths or else multiple 2-beat transactions are produced, and when there are multiple transactions produced the burst type and length will determine what the start addresses will be for each transaction created.
Note that the BP131 AXI DownSizer component is no longer available as a standalone product and instead its functionality has been built into the NIC-400 AXI interconnect product, where you can if required, generate a standalone bridge to implement any required conversion function or combination of functions (protocol conversions, data width conversions, clock domain crossings).