"The WSTRB[n:0] signals when HIGH, specify the byte lanes of the data bus that contain valid information. Thereis one write strobe for each eight bits of the write data bus, therefore WSTRB[n] corresponds toWDATA[(8n)+7: (8n)].A master must ensure that the write strobes are HIGH only for byte lanes that contain valid data." -- --> THIS WHAT GIVEN IN AXI4 PROTOCOL SPECIFICATIONSLike I am having a confusion here what exactly it indicates like i am presenting the possible use cases and could someone tell me whether my assumptions are correct!!
I am taking WDATA BUS width as 128 bits wide and WSTRB corresponds to 16 bits USE CASE- IMASTER SLAVE
ADDR:0Transfer Size: 16 bits Slave will receive data as 2 like strb 1 indicate like [7:0] are valid bytesTransfer Length: Single beatData to be written is 2Burst type: FixedStrobe here is 1
USE CASE- II
MASTER SLAVE
ADDR:0Transfer Size: 16 bits In this case strobe is 2 therefore [15:8] is a valid byte and slave would read the value as 0 or the master will tend to shift the data "2" in [15:8] and the slave would read that shifted dataTransfer Length: Single beatData to be written is 2Burst type: FixedStrobe here is 2
USE CASE- IIIMASTER SLAVE
ADDR:0Transfer Size: 16 bits like strb 3 indicate like [7:0] and [15:8] are valid bytes and so slave would read data as 02Transfer Length: Single beatData to be written is 2Burst type: FixedStrobe here is 3
Could someone tell me out of these three test cases which test case is correct and if possible could you give me a solution for it....As Wstrobe indicates these are the valid bytes in the particular data bus and whether master should often obey the strobe signal and based on that it should write the data into the slave memory locations..