Arm 22nm TSMC 22ULL-GL memory power management

Dear Sir or Madam,
    I am trying to confirm the potential risk of powering up/down memory. Our soc design implements Arm 22nm TSMC 22ULL-GL memory (TS83Cx00x series). In order to do proper power management with memories, I've being looking into Application Note <Arm Artisan 22nm TSMC 22ULL-GL Memory Power Mangement>. The application note stated clearly that there should be a power supply sequence for VDDCE and VDDPE (when powering up, power up VDDCE first, then VDDPE; when powering down, shut down VDDPE first, then VDDCE). Since such power sequence requires delicated PMU design and also have influence to our PMIC spec, I am interested to understand the risk if we powering up/down VDDCE and VDDPE simultaneously?
    Thank you for your time and I look forward to hearing from you.
Yours sincerely,