I am having trouble understanding the behavior of the HTRANS busy state mentioned in the specification(ARM IHI 0033A), and I am feeling confused. I would like to explain my situation and request assistance in understanding it. I will explain a detailed situation based on the diagram below.
T0 - T1 The 4-beats read operation start with a NONSEQ TransferT1 - T2 Master inserts a busy trasnsfer and slave asserted the HREADY signal from 1 to 0 in order to handle the data read operation. T2 - T3 The slave asserts HREADY to 1 when the data is ready, while the HTRANS of the master remains in the busy state.
In my opinion, during the T2-T3 interval, HREADY is asserted to 1 as a response to the transaction that occurred between T0-T1, indicating that D0_a1 is valid.
However, accoding to the spec description , this transfer must be ignored by slave. Therefore, from the master's perspective, since Htrans is in a busy state, the value of D0_a1 will be considered invalid and ignored.In other words, during the T4-T5 interval when Hready is 1 and Htrans is not in a busy state, the value of D2_a1 becomes the valid data for NSEQ.
so, I have a question about the behavior of MASTER in HTRANS busy state when designing a slave.Which interval's value in the given diagram is considered valid for the response of HTRANS=NSEQ in the T0-T1 interval?
I have fully understood your explanation regarding the question I asked.
Thank you for your response.