Hi...I have 2 questions from AHB
1) What does "1kB address boundary" in AHB means ? Does it mean that each slave can have only 1024 locations ? For example slave1 can have only 1024 locations starting from address 0 to 1023 & slave2 also have 1024 locations starting from address1024 to 2047 & so on for other next slaves ?
2) What does the following line means "All transfers within a burst must be aligned to the address boundary equal to the size of the transfer. For example, word transfers must be aligned to word address boundaries (that is A[1:0] = 00), halfword transfers must be aligned to halfword address boundaries (that is A = 0)" ? How did they decided that with word transfer (32 bit) will be aligned to 32 bit address boundaries if A[1:0] =00. Please give one example.
1) just means that bursts cannot cross a 1kB boundary.
1kB is then the smallest size the AHB decoder will decode (I think this means decoding down to HADDR worst case), but slaves can be multiples of 1kB. So slave1 could have addresses at 0 to 2047 in your example.
As the CPU or SW writer doesn't necessarily know the physical makeup of the memory map, you doesn't know where one physical slave ends and the next starts. If you don't have an address boundary defined that bursts must not cross you could then see a burst starting on one slave with a NONSEQ access and HBURST perhaps indicating a specific number of transfers, and this burst then crossing to a new physical slave which sees a "new" burst start with a SEQ access and an HBURST value that doesn't relate to the number of transfers remaining to be performed. So the boundary definition ensures the slave sees a burst start with a NONSEQ, and complete the required number of HBURST defined transfers (ignoring legal early burst termination scenarios).
1kB was chosen as a compromise between wanting to support small slaves (needing a smaller boundary) and supporting longer bursts (needing a larger boundary). When AHB was first developed you probably had 32 or 64-bit data buses, so a 16-beat 64-bit burst would cover 128 bytes, giving you quite a bit of flexibility in the address the burst could start at and still remain within the 1kB boundaries.
Comparing this to the later developed AXI where you have 4kB boundaries specified, by this time wider data buses were common, so a 16-beat burst of 128 or 256-bit transfers would soon hit the 1kB boundary, hence 4kB being chosen as the compromise boundary.
2) the AHB protocol doesn't support unaligned transfers. So if you are performing 32-bit transfers, HADDR will be a 32-bit aligned value, meaning HADDR[1:0] will be 2'b00.
If the SW being executed on the CPU attempts to access a 32-bit value at a non-32-bit-aligned address, the AHB interface on the CPU will need to convert this SW transfers into 2 AHB accesses to cover the 2 32-bit aligned values the SW unaligned access wanted to access.
Thanks a lot Colin for responding.