If I'm building an SoC with multiple, heterogeneous cores (say, some M3s, R5s and A's), is it better to use the processor intergration layers (PIL) that have already encapsulated the ETMs and CTIs?
Or would it be better to just use the raw cores and create my own debug infrastructure?
It seems like there will be redundancies if I use the PILs but if I build my own I can be more regular.