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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3599 Questions
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  • Answered

    Configuration of SVE Vector Length on ARM N2 Processor 0

    • EL1
    • EL3
    • EL2
    • Vector
    • EL0
    • Armv8-A
    • NEON
    • SVE
    • Armv9
    2249 views
    3 replies
    Latest 10 months ago
    by vstehle Arm Employee Badge
  • Answered

    How to find definitions for arm_sve.h intrinsics? 0

    • NEON
    • GNU Arm
    1833 views
    2 replies
    Latest 10 months ago
    by DavidAl
  • Not Answered

    TCMRETRY 0

    1486 views
    3 replies
    Latest 10 months ago
    by depei zhang
  • Not Answered

    corstone-201 RTL generation 0

    528 views
    0 replies
    Started 10 months ago
    by Sharath HS
  • Answered

    Question about AXI K protocal "A6.3.4 Manager ordering guarantees" 0

    • AXI
    • CHI
    1553 views
    2 replies
    Latest 10 months ago
    by Ming Gao
  • Not Answered

    ARMv7 Cache Question 0

    • Armv7-A
    • Cache coherency
    510 views
    0 replies
    Started 10 months ago
    by prahsman
  • Answered

    AXI-5 User Loopback Signaling use cases? 0

    • AXI
    1632 views
    2 replies
    Latest 10 months ago
    by Rishi Cheriyan
  • Not Answered

    Losing Debugger Control When Booting Cortex-A53 on S32G2 (Type 1 Hypervisor) +1

    • Cortex-A53
    • GICv3/v4
    • Cache
    • Armv8-A
    • Debugging
    • Hypervisor
    • gic500
    • Baremetal
    1193 views
    1 reply
    Latest 10 months ago
    by pcarmo
  • Suggested Answer

    Is there any way to change the polarity of tdo_en port in M33 IP core? 0

    1152 views
    1 reply
    Latest 10 months ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    A9 Cp15 issue 0

    • a9
    • boot
    • Cortex-A
    • cp 15
    1277 views
    2 replies
    Latest 10 months ago
    by prahsman
  • Suggested Answer

    What is the difference between Exclusive access in AXI 3 and AXI 4 ?How does Lock access is merged to exclusive access in AXI4? 0

    1384 views
    1 reply
    Latest 11 months ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    AXI PROTOCOL 0

    2253 views
    4 replies
    Latest 11 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Narrow Byte Transfers on AHB2APB Bridge 0

    • APB
    • AHB2APB
    • AHB5
    • NARROW_BURST
    1214 views
    1 reply
    Latest 11 months ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    How to change total compute DRAM size? 0

    857 views
    1 reply
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to distribute single one SPI to multi PE concurrently in GIC-600 ? 0

    1293 views
    1 reply
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Relation between Load/Store Physical Address (PA) and L1, L2, L3 Cache Set Number 0

    • Cache Set Number
    • Physical Address (PA)
    571 views
    0 replies
    Started 11 months ago
    by Meng-Yu Tsai
  • Not Answered

    Capture R5F lockstep mismatch error as interrupt in PLM 0

    522 views
    0 replies
    Started 11 months ago
    by Rob Wan
  • Not Answered

    Cortex A9 Boot operation Sequence 0

    • Cortex-A9
    • Memory Management Unit (MMU)
    • Baremetal
    1001 views
    1 reply
    Latest 11 months ago
    by prahsman
  • Not Answered

    how avoid q registers being used for single ldr? 0

    • Exception Handling
    • Cortex-A53
    • Compilers
    • alignment
    607 views
    0 replies
    Started 11 months ago
    by WatterCutter
  • Answered

    Cortex-R5F hang upon IRQ reception 0

    • Cortex-R5
    • irq
    • Armv7-R
    • hang
    1599 views
    2 replies
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
<>
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