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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    Cortex-R5F hang upon IRQ reception 0

    • Cortex-R5
    • irq
    • Armv7-R
    • hang
    1362 views
    2 replies
    Latest 9 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Cortex-R52+ asynchronous external abort 0

    • abort
    • Cortex-R52+
    1632 views
    3 replies
    Latest 9 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    RK3588 chipset support 0

    1878 views
    1 reply
    Latest 9 months ago
    by Krotti42
  • Not Answered

    How to use the recent MMLA Instructions Efficiently [Required Data Layout]? 0

    • Armv8.6-A
    • intrinsics
    • NEON
    • Memory
    642 views
    0 replies
    Started 9 months ago
    by FabianSchuetze
  • Answered

    any feature of processor needed for instruction stur? 0

    • Cortex-A53
    • Instruction Sets
    • Armv8-A
    1085 views
    1 reply
    Latest 9 months ago
    by vstehle Arm Employee Badge
  • Not Answered

    Cortex-R52+ Undefined exception 0

    • Exception Handling
    • Debugging
    • Cortex-R52+
    568 views
    0 replies
    Started 9 months ago
    by Grace WANG
  • Answered

    Is there have any latest news about CMN700 AE (Automotive Enhanced)? +1

    1233 views
    2 replies
    Latest 9 months ago
    by Z Z
  • Suggested Answer

    PWM capacity of STM32F7xx 0

    1114 views
    1 reply
    Latest 9 months ago
    by Edd Dan
  • Not Answered

    Debugging Challenges in RDP Level 1 Mode on CORTEX M0+ 0

    • Cortex-M0
    • SWD
    • Debug and Trace
    567 views
    0 replies
    Started 9 months ago
    by Edd Dan
  • Answered

    Cortex-R52 GICv3 Interrupt1023 0

    • Interrupt Handling
    • GICv3/v4
    • irq
    • FIQ
    • Cortex-R52+
    4361 views
    12 replies
    Latest 9 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Does R52/R52+ support thumb-2 ? 0

    • Cortex-R52
    • Thumb2
    • Cortex-R52+
    996 views
    1 reply
    Latest 9 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Pack high bit of every byte in ARM NEON, for 64 bytes like AVX512 vpmovb2m? 0

    • NEON
    1729 views
    2 replies
    Latest 9 months ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Method for Acquiring and Decoding ETM Trace Data Less Than 16 Bytes Just Before Program Break +1

    1005 views
    1 reply
    Latest 9 months ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Pending Interrupt is signaled even when interrupt is masked 0

    • Cortex-A
    • Interrupt
    • Linux
    1419 views
    2 replies
    Latest 9 months ago
    by Lijian Huang
  • Not Answered

    Which ARM Processor with Gigabit Ethernet Support Should I Choose? 0

    • Arm7
    • Arm9
    • a53
    • IDEs and Tool Suites
    540 views
    0 replies
    Started 9 months ago
    by Bora Dikmen
  • Not Answered

    Need for DSB and ISB for interrupt pending to take immediate action. 0

    • Cortex-M7
    • Cortex-M4
    1039 views
    1 reply
    Latest 9 months ago
    by asts
  • Not Answered

    About unsupported exclusive or atomic access issue 0

    1214 views
    2 replies
    Latest 9 months ago
    by Wesley Hwang
  • Suggested Answer

    Cortex-R52+ goes to abort when writing CPSR 0

    • CPSR
    • abort
    • Cortex-R52+
    1150 views
    1 reply
    Latest 10 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    In ARM CHI spec, what is the difference between using ReadShared with exclusive access vs ReadUnique? 0

    • CHI
    • coherency
    3820 views
    6 replies
    Latest 10 months ago
    by Ola Liljedahl Arm Employee Badge
  • Answered

    Axi ARSIZE with narrow subordinates 0

    • APB
    • APB Peripherals
    • AXI
    • AXI4
    • arsize
    • bridge
    2322 views
    5 replies
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
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