I understand that the TCM (Tightly Coupled Memory) address can be assigned by the user as shown below, so I know the method for TCM base address assignment:
Example 8-1: Setting TCM locationDSB ; Data synchronization barrierMOV r0, #0x800000001 ; Set base address, with enable bit setMCR p15, 0, r0, c9, c1, 0 ; Write TCM region registerISB ; Instruction synchronization barrier
However, for the cache system (both I-Cache and D-Cache), the base addresses are not user-configurable in the same way. I want to know whether it is possible to insert specific data into the cache to corrupt it for cache testing purposes. To perform such a test, I think I need to know how the cache address is assigned.
I came across a cache enable example using CP15 registers to enable the I-Cache and D-Cache. Here's how it is done by writing to the System Control Register (SCTLR):
MRC p15, 0, r0, c1, c0, 0 ; Read SCTLRORR r0, r0, #(1 << 12) ; Set bit 12 to enable I-CacheORR r0, r0, #(1 << 2) ; Set bit 2 to enable D-CacheMCR p15, 0, r0, c1, c0, 0 ; Write SCTLR
But It seems there isn't explicit information available about cache addresses. How, then, is the cache address assigned on the R5?
Under "normal" operation, software marks which addresses are cacheable (e.g. DRAM). The caches are then naturally populated as the program runs, with lines being evicted and filled as a result of misses/prefetches/maintenance operations. In that sense, software only indirectly controls what is in the cache - it says what is cacheable, but the exact contents at any given time is down to recent accesses.
It is possible to directly access the cache RAMs via the AXI-S port, that's described here:
https://developer.arm.com/documentation/ddi0460/d/Level-Two-Interface/AXI-slave-interface/AXI-slave-interface-for-cache-RAMs?lang=en
And:https://developer.arm.com/documentation/ddi0460/d/Level-Two-Interface/Accessing-RAMs-using-the-AXI-slave-interface/Cache-RAM-access?lang=en
However, this isn't intended for normal use, rather for testing. And the AXI-S access can't be active at the same time as the caches being used for regular operation (see the TRM page I linked to for more details).
Thank you, Martin.Thank you for letting me know. Actually, what I'm most curious about from your response is how to find the base address of the I-Cache/D-Cache.Following the information from the link you provided earlier, I understood that I can access the base memory address of the TCM by specifying it in the memory map, as shown in the following example:
Example 8-1 Setting TCM location
DSB ; Data synchronization barrier MOV r0, #0x800000001 ; Set base address, with enable bit set MCR p15, 0, r0, c9, c1, 0 ; Write TCM region register ISB ; Instruction synchronization barrier
However, there was no explanation regarding the base address of the I-Cache/D-Cache, which makes it difficult to understand.Is there a way to find out the base address of the I-Cache/D-Cache?If I could at least know the relationship between the addresses of the TCM and Cache, I could make an educated guess, but I don't know of any specific way to find out, so I am asking for your help.
The information I have found includes ikvalidate.cfg and cortexr5_params.v.I can only assume that since the basic cache size is set to 32kB, the address 0x8000 might apply.
ikvalidate.cfg
cortexr5_params.v
Not sure you are a Cortex-R5 SoC designer or not but you provide a verilog file screenshot.
Cortex-R5 TRM says: "Each TCM interface has a dedicated base address that you can place anywhere in the physical address map, and must not be backed by memory implemented externally. The ATCM and BTCM interfaces must have separate base addresses and must not overlap."The SoC designer should know where the base addresses are.