Cache Coherency for memory using SMMU V3

Adithya SM 4 days ago

Hi,

I have set up the MMU for my ARM A55 core treating the RAM as normal memory with inner and outer cache enabled. I want to use the SMMU similarly.
the outcome I expect is to have a DMA operation that uses the SMMU to not having to deal with cache invalidation or writebacks.
Following are the configurations that I have set.

Stream table

SHCFG = 0x3
DCP = 0x1
DRE = 0x1

Context Descriptor

MAIR0 = 0xFF4400

Translational Table
MAIR index selected is 2.