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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3635 Questions
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  • Not Answered

    [ARM R52+] GIC distributor on R52+ with DCLS 0

    • GICv3/v4
    • Armv8-R
    1184 views
    2 replies
    Latest over 1 year ago
    by ShihHsun Chang
  • Not Answered

    Question about ITS Retry Behavior after Stalled MAPD Command 0

    1106 views
    2 replies
    Latest over 1 year ago
    by steve jeong
  • Suggested Answer

    AXI4 ordering Model. 0

    • AXI4
    1265 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

    • ACE
    1282 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

    • Cortex-R5
    2383 views
    6 replies
    Latest over 1 year ago
    by ele
  • Not Answered

    Is there any way to use 2-DSU IPs in a same NI-Bus ? 0

    • DSU-120
    • DSU
    430 views
    0 replies
    Started over 1 year ago
    by Sangu Park
  • Answered

    Secure Mode Switching in R5 0

    • cortexr5
    1041 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Request for Configuration and Usage Guide of PERIPH_PORT in Corinth 0

    • Cortex-A55
    • Cortex-A
    429 views
    0 replies
    Started over 1 year ago
    by yiduan su
  • Answered

    What will happen when cacheline is mismatch 0

    • Cache
    • Cache Management
    • Cortex-A
    • Cortex-M
    1347 views
    2 replies
    Latest over 1 year ago
    by junhao.wang
  • Answered

    Does Cortex-A53 support Separate Start Address? 0

    • Cortex-A53
    1084 views
    1 reply
    Latest over 1 year ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    625 views
    0 replies
    Started over 1 year ago
    by Adithya SM
  • Suggested Answer

    Halt-on-debug scenario, halt the system counter when halting. 0

    • Cortex-A9
    • CoreSight Debug and Trace
    • Armv8-A
    • Cortex-A
    2178 views
    5 replies
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

    1945 views
    5 replies
    Latest over 1 year ago
    by Jake Zhao
  • Answered

    How to generate LPI with ITS? 0

    1190 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    943 views
    1 reply
    Latest over 1 year ago
    by steve jeong
  • Answered

    Cortex-R52+ asynchronous abort 0

    • abort
    • Cortex-R52+
    1610 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

    • AMBA
    • AXI
    467 views
    0 replies
    Started over 1 year ago
    by Manikanta Kopparapu
  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
    • optee
    • jetpack
    2245 views
    0 replies
    Started over 1 year ago
    by Niklas Flink
  • Answered

    How to mapping MSI (LPIs) in Linux kernel 6.12.y ? +1

    2534 views
    3 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Multi-Master APB Subsystem 0

    529 views
    0 replies
    Started over 1 year ago
    by Abdelrahman Ehsan
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