Halt-on-debug scenario, halt the system counter when halting.

Dujiao Zhang 12 days ago

From "I2.2.2 Halt-on-debug", When the CNTCR.HDBG bit is set to 1, and the Halt-on-debug signal is implemented and asserted, the system counter is halted. Otherwise, the system counter ignores the state of this signal.

What are the practical use cases for pausing the system counter through an external debugger? When is it necessary to pause the counter through cross-triggering?

Top replies

Zhifei Yang 11 days ago +1

Let's assume one scenario in a multi PE system, if one core is halted by the debugger while the system counter ( or global timer or system timer in other naming conventions ) continues to increase, if...
Zhifei Yang 4 days ago in reply to Dujiao Zhang +1 suggested

It will affect other cores if the global counter is halted. So the developer should know and balance the debugger impact vs the debugger actions he will take.