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Hi,arm experts，
Most A series processors have a 64-byte cacheline, while M series processors have a 32-byte cacheline. If an M series processor initiates a 32-byte cacheline coherent access to an A series processor through the ACP, what will happen? Will the A series processor retrieve the full 64-byte data? If there is a system cache downstream of the M series processor, and the cacheline length of the system cache is also 64 bytes, will the result be similar to the previous one?
Thank you a lot for your help
Hi junhao.wang,
If the requests are cacheable and the Cortex-A allocates the cacheline in its cache for future use then it will indeed have to retrieve the full 64B data.
Note that the ACP port of a Cortex-A can typically not handle all types of requests; refer to the Cortex-A53 TRM ACP section for example and to the AMBA specification ACE5-LiteACP protocol. There are two options to transfer 32 bytes through ACP: two 16B transfers or a single 64B transfer.
Also note that the ACP port is meant for an I/O-coherent accelerator; the Cortex-A would not be able to snoop the cache of a Cortex-M attached there.
Hi,vstehle,
Thank you for your answer, and if my cortex-M processor work as an IO coherent Request Node in system with last level cache(or CI-700, for example), when processor excute a cache eviction, or cacheable read from DDR, all transaction are 32 byte, what will CI-700 work like? Will it cause bandwidth waste?
Thank you