hi sir,
a soc with a no-cache MCU, which have 200MHz main clock. And other cortex-a cores with L1/L2 cache enabled, which have about 1GHz main clock.they shares an unique DDR memory controller and DDR memories. The ddr controller have only one port through main interconnect.
It says The MCU will take memory access through the main interconnect, in EVERY instruction exec. clearly, even more memory access in ld/st.so, does the MCU introduce huge latency to cortex-a cores, when L2 cache interacting with DDR memory?
Is there have a cache-like buffer (like only-one-cache-line etc.) in the main interconnect or DDR controller, so that it can merge memory access into a burst?
thanks a lot