Hello,
I have a question about the debugger functions related to CMSIS-DAP and CoreSight.
I have a Cortex-M4 and M33 CPU board, and I can read 1KB of data from each target board using OpenOCD.
I currently try to increase the buffer size to reduce communication overhead.
For the M4 target board, I was able to read 4KB of data correctly using the DAP Transfer command "06h/DAP_TransferBlock".
However, for the M33 target board, I was unable to read the data I had written correctly using the same command.
Specifically, the first 1KB was correct, but the same data was repeated to make 4kB.
I wonder if there is a problem with the RAM size that can be used by the DAP commands of the M4 and M33, but I don't know how to deal with it.
Is the RAM size that can be handled by the DAP command of the M33 smaller than that of the M4?
If you have any information, please let me know.
Thank you.
For the M33 board, can you read the 1KB data in 4 times instead of 4KB in one time? Of course, you need to add address offset for the second/third/forth 4KB reading.
What is the result?
Hello Zhifei Yang,
When I read 4KB of data in 1KB increments using the M33 board, the data that was written could be read.
When using the "DAP_TransferBlock/06h" command to read an amount greater than 1KB at a time (for example, 4KB), the first 1KB can be read correctly.However, the remaining 3KB is a repetition of the first 1KB, and the written data cannot be read correctly.
This may not be a RAM issue but a CoreSight ETM-M33 specification, but I have not been able to find any related documentation.
Both the Cortex-M4 board and Cortex-M33 board use the same DAP_SWD port or DAP_JTAG port? Or any difference?CMSIS_DAP uses the same CMSIS_4 or CMSIS_5 version for the two boards?Any board uses the slow cycle or fast cycle setting?
You may raise one ticket here https://github.com/ARM-software/CMSIS_5/issues with more details found.
I use the DAP software included in CMSIS_5 to access the devices via the DAP_SWD port.I test the same software by simply replacing the board.
While reading the Technical Reference Manual for each device, I came across a passage that interested me.
The symbol AddrInc[5:4] in the CSW register (AHB-AP) contains the following statement.
I wonder if it has something to do with the amount of data that "DAP_TransferBlock/06h" can transfer?
Arm Cortex-M4 Processor Technical Reference Manual Revision r0p1AHB-AP programmers model"Increments and wraps within a 4KB address boundary, for example from 0x1000 to 0x1FFC."
Arm Cortex-M33 Processor Technical Reference ManualAHB-AP Control/Status Word register, CSW, 0x00"Incrementing and wrapping is performed within a 1KB address boundary, for example, for word incrementing from 0x1400-0x17FC."
Yes, nice capture! Looks reasonable.
Better to raise one CMSIS_5 issue in github for further analysis.
Thank you for your reply.
Since this is about usage rather than an issue, I don't think it's necessary.Thank you for your suggestion.