Will these two different data storage methods and MPU settings affect CPU efficiency?

Possibly.  Two examples to think about.

Direct branches (those which are PC relative) have a maximum range, exactly what that range is depends on the instruction set and variant of the branch.  You've not given the sizes of those regions, but fragmenting the instruction space _might_ result in more branch targets being outside of the branch range.  In which case the linker will need to insert veneers (small fragments of linker generated code) to extend the range for affected branches.  Whether that has any meaningful impact is going to depend on how many veneers the linker needed to insert and how often the veneered branches get called.

Then there's possible micro-architecture effects, which will be specific to a given processor.  Typically, data regions are marked as execute never.  The processor cannot prefetch instructions from regions marked as execute never.  Fragmenting the instruction space _might_ make some forms of prefetching harder/less efficient.  Even if the processor's ability to prefetch were impacted (which again, depends on the specific micro-architecture), whether that translated to noticeable effects is going to depend a lot on the software.  If the execution mostly stays in one of the fragmented blocks and rarely moves between blocks then there might not be any appreciable difference.

In summary: The layout of code and data can - in some circumstances - impact performance/efficiency.

Possibly.  Two examples to think about.

Direct branches (those which are PC relative) have a maximum range, exactly what that range is depends on the instruction set and variant of the branch.  You've not given the sizes of those regions, but fragmenting the instruction space _might_ result in more branch targets being outside of the branch range.  In which case the linker will need to insert veneers (small fragments of linker generated code) to extend the range for affected branches.  Whether that has any meaningful impact is going to depend on how many veneers the linker needed to insert and how often the veneered branches get called.

Then there's possible micro-architecture effects, which will be specific to a given processor.  Typically, data regions are marked as execute never.  The processor cannot prefetch instructions from regions marked as execute never.  Fragmenting the instruction space _might_ make some forms of prefetching harder/less efficient.  Even if the processor's ability to prefetch were impacted (which again, depends on the specific micro-architecture), whether that translated to noticeable effects is going to depend a lot on the software.  If the execution mostly stays in one of the fragmented blocks and rarely moves between blocks then there might not be any appreciable difference.

In summary: The layout of code and data can - in some circumstances - impact performance/efficiency.