I wanted to control the system by switching between Secure and Non-Secure modes while using the R5 processor. However, when I checked the TRM document, I found the following statement:
"All transactions are non-secure data accesses." Does this mean that all AXI transactions from the R5 processor are Non-Secure?
Is it impossible to switch between Secure and Non-Secure modes in R5? If so, how can security partitioning functions like TZPC be utilized?
ele said:I wanted to control the system by switching between Secure and Non-Secure modes while using the R5 processor.
I'm afraid that is not possible. The Cortex-R5 only supports a single Security state - therefore there's nothing to switch between.
ele said:"All transactions are non-secure data accesses." Does this mean that all AXI transactions from the R5 processor are Non-Secure?
The quote you are referring to is specifically about the peripheral port.
More generally, Armv7-R doesn't have a way for software to control the outputted Physical Address Space (PAS). If there is a way for software to control whether a Secure or Non-secure physical address is accessed, this would be from some system/SoC specific logic outside of the core.