Hello,
I'm currently working on a Bluetooth SoC design using the Cortex-M33 processor. I noticed that the M33 core includes cache enable control signals, but I couldn’t find explicit mention of an integrated instruction cache (I-Cache) block in the standard IP deliverables.
Could someone please clarify:
Does ARM provide an integrated I-Cache as part of the Cortex-M33 RTL package?
If not, is it expected that licensees implement their own instruction cache controller externally?
Are there configurable options to include I-Cache in the M33 during IP integration?
Any guidance or documentation reference would be greatly appreciated.
Thank you!
The Cortex-M33 does not include an internal cache. However, it provides all the necessary signals to support the integration of an external cache if needed. The ARMv8-M architecture with PMSA (Protected Memory System Architecture) supports distinct memory attributes for inner and outer Normal memory.
In typical ARM processors, inner attributes correspond to internal cache behavior, whereas outer attributes are used when interfacing with external memory systems. Since the Cortex-M33 lacks an internal cache, the outer attributes are directly reflected on the AHB5 bus via the HPROT signal. Meanwhile, the inner attributes are conveyed on the AHB5 user-defined bus signal HINNER, using the same encoding as HPROT[6:2]. This allows a system to implement and utilize an external cache if desired.
The HPROT[6:2] signals are managed by the Memory Protection Unit (MPU). If the MPU is disabled or no regions are configured, these attributes default to those defined by the ARMv8-M architectural memory map.
For reference, the CG092 is a simple instruction-side cache that can be used with the Cortex-M33. Additional information about the CG092 and the Arm Corstone-201 Foundation IP is available here:
developer.arm.com/.../