Hello,
I'm currently working on a Bluetooth SoC design using the Cortex-M33 processor. I noticed that the M33 core includes cache enable control signals, but I couldn’t find explicit mention of an integrated instruction cache (I-Cache) block in the standard IP deliverables.
Could someone please clarify:
Does ARM provide an integrated I-Cache as part of the Cortex-M33 RTL package?
If not, is it expected that licensees implement their own instruction cache controller externally?
Are there configurable options to include I-Cache in the M33 during IP integration?
Any guidance or documentation reference would be greatly appreciated.
Thank you!