AXI4 ordering Model.

Rajneesh Mishra said:

Here I had few question on the highlighted spec which is unclear to me by reading.

1) For the Same ID the initiated request should reach the target in a same order in which they are issued If the request is to peripheral device or to the memory device  with overlapping address.
2) If a master issues a Transaction in one direction and it has issues another request without getting the response in the other direction then there is no ordering guarantee between two transaction

Both of the line from the spec seems to be conflicting to me unless 2nd one is applicable only for the request with different ID.

I would recommend referring to the latest version of the AXI Specification (Issue K) - this section has been re-written to the be clearer.

The section you highlighted should be read in the context of the previous paragraphs. Different directions refers to the separate read and write channels, and so a read and a write with the same AxID value are ordered with respect to each other.

The rule is that in a single direction, to the same peripheral, accesses with the same AxID will be received in the order of issue.  This means that reads with the same ARID will be ordered, and writes with the same AWID will be ordered.  However, reads and writes are not ordered against each other, even if they have the same AxID, and so you need to wait for a previous response to get ordering between reads and writes.

There should be no conflict in these statements.

Rajneesh Mishra said:

As per my understanding:

1) if there are 2 request with  Address A0 and A1 and ID is same for both then request with address A0 should reach the target device 1st followed by request with address A1 given Address with A0 request is initiated first by the initiator followed by address with A1 request.

2) if there are 2 request with the same address A0 and the same ID is used  for both of the request then whichever request is launched from the Initiator first should reach the target first In case of memory transaction.

3) if there are 2 request with  Address A0 and A1 and ID is same for both then there is no ordering requirement for the request given the A0 and A1 address transaction doesn't have overlapping address in case of memory transaction.

Can anyone help me with above points ?

Point 1 and 2 are correct, but only if those two requests are on the same channel, and to the same peripheral.

Point 3 depends on whether the access is to a single peripheral or not.  If it is to a single peripheral, then these must remain ordered.  In other cases, these are not guaranteed to arrive in the order of issue.