I am looking for practical applications of various transaction types in real-world ARM-based systems. For example, READONCE is commonly used in a display controller when reading a cached frame buffer. Similarly, how are other transaction types like ReadNoSnoop, WriteNoSnoop, ReadOnce, ReadClean, ReadNotSharedDirty, ReadShared, ReadUnique, CleanUnique, MakeUnique, CleanShared, CleanInvalid, MakeInvalid, WriteUnique, and WriteLineUnique used in actual hardware implementations?
Can anyone share insights or examples of how these are applied in systems like GPUs, memory controllers, or multi-core processors?
It is difficult to have a mapping table to summarize all the transaction types vs real applications.
Can we know under which scenario, you need to have this detailed table?General speaking, there are high level layers you can dig into if you want. Take cache instructions as example.
flush_cache_range(): Flushes (cleans) a range of cache lines.
flush_cache_range()
invalidate_cache_range(): Invalidates a range of cache lines.
invalidate_cache_range()
flush_dcache_page(): Ensures data is written back to memory.
flush_dcache_page()
dma_map/unmap_*(): Used for DMA operations where cache coherency is required.
dma_map/unmap_*()
DC CIVAC (Data Cache Clean and Invalidate by Virtual Address to Point of Coherency): Ensures a cache line is cleaned (written back to memory) and invalidated in other caches.
DC CIVAC
DC CVAC (Data Cache Clean by VA to PoC): Cleans but does not invalidate.
DC CVAC
DC IVAC (Data Cache Invalidate by VA to PoC): Invalidates but does not clean.
DC IVAC
e.g. When an ARM core executes a cache maintenance instruction (e.g., DC CIVAC), the following happens:
The core’s cache controller detects the operation.
If the cache line is dirty, it is written back to memory (Clean).
The AXI/ACE bus broadcasts an invalidation request to other caches (Invalid).
Other cores snoop the request and invalidate their copies of the cache line.
The memory controller ensures the latest data is visible to all agents.
Please note for different CPU IPs or interconnect IPs, there may be slight behavior difference.