I am utilizing the APB2 protocol without the PSTRB. As I am building a bridge from APB to my sram that has a bus WE bus width of 4 bits, May I know if there is a way to provide 4 bits of WE to my ram through this protocol from the cpu? I am adopting the byte-addressing system, so i was wondering if it is possible to use paddr to achieve this purpose.
For APB2 the assumption is that any access is to the full width of the data bus, so you would need to assert all sram WE bits for any write access. This isn't a "byte-addressing system" unless the registers you are accessing are on an 8-bit data bus.
If you did want to implement support for writes to update just one byte of the APB sram, you would need to code this into the APB peripheral design, with a specific address set aside to update just that one byte.
So if your APB sram locations were 32-bits wide, you could have them accessed at addresses 0x0, 0x4 etc, and then also implement a byte write address space for those same locations, so...
0x100 updating PWDATA[7:0] of the 32-bit sram at 0x0
0x104 updating PWDATA[15:8] of the 32-bit sram at 0x0
0x108 updating PWDATA[23:16] of the 32-bit sram at 0x0
0x10C updating WDATA[31:24] of the 32-bit sram at 0x0
0x110 updating PWDATA[7:0] of the 32-bit sram at 0x4
0x114 updating PWDATA[15:8] of the 32-bit sram at 0x4
0x118 updating PWDATA[23:16] of the 32-bit sram at 0x4
0x11C updating WDATA[31:24] of the 32-bit sram at 0x4
...and so on.
But it would be a lot simpler to just implement the APB4 protocol and have the byte strobes as part of the protocol.