Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    About CPU behavior when it receives error response signal during reading or writing 0

    1579 views
    2 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Understanding ARM core performance 0

    1239 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Not Answered

    Understanding ARM core performance 0

    595 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Suggested Answer

    Cortex A55 : Hotplug of secondary core 0

    • Cortex-A55
    • Armv8-A
    • Cortex-A
    2587 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    How peripherals are accessible between NW and SW? 0

    • SMMUv3
    • Peripheral Controllers
    • TrustZone
    1078 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    What does "Bit-Band Operation of Different Data sizes" meaning? 0

    • Cortex-M
    807 views
    0 replies
    Started over 2 years ago
    by shadow3d
  • Answered

    Does NIC-400/AXI provide full theoretical bandwidth 0

    • CoreLink NIC-400
    • AXI4
    1302 views
    1 reply
    Latest over 2 years ago
    by Ryleigh Sawayn
  • Not Answered

    What A53 interrupt signal should I use for watchdog timeout? 0

    • Cortex-A53
    1351 views
    1 reply
    Latest over 2 years ago
    by Ryleigh Sawayn
  • Answered

    Migration from Cortex M4 to Cortex R5F 0

    • Software
    • Cortex-R5
    • Cortex-M4
    2823 views
    3 replies
    Latest over 2 years ago
    by Ryleigh Sawayn
  • Not Answered

    Cortex-A53 PMU: Read Allocate Mode Event Definition (BUS_ACCESS erratum work-around) 0

    • Cortex-A53
    1201 views
    0 replies
    Started over 2 years ago
    by rayman_de
  • Not Answered

    pl330 scatter-gather transfer 0

    1302 views
    2 replies
    Latest over 2 years ago
    by GuillaumeB
  • Answered

    Reading Cortex-A9 CNTFRQ register using ARM Compiler 5 inline assembly 0

    • Cortex-A9
    • Arm Assembly Language (ASM)
    • Arm Compiler 5
    3127 views
    7 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Cortex-A9 , get CPU frequency , bare metal 0

    • Cortex-A9
    • Baremetal
    2243 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Is it possible to disable L2 Cache in CA-55 core? 0

    • Cortex-A55
    1334 views
    2 replies
    Latest over 2 years ago
    by chaitanya.k
  • Answered

    question about arbitration scheme of AHB bus matrix 0

    • CMSDK
    • SoC FPGA
    • DMA Devices
    • Bus Architecture
    • AMBA 2 AHB Interface
    1905 views
    2 replies
    Latest over 2 years ago
    by JJ HUA
  • Answered

    DEFLAGS on Cortex A9 FPU 0

    1314 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Exception entry stacking on Cortex-M7, not possible to stack onto Main stack at any case? 0

    • Cortex-M7
    1272 views
    0 replies
    Started over 2 years ago
    by Zoltan
  • Not Answered

    What is the default FPU in ARMv8? 0

    • AArch64
    • Armv8-A
    • NEON
    • Floating Point
    • AArch32
    2356 views
    2 replies
    Latest over 2 years ago
    by pedrobotelho15
  • Not Answered

    What are the risks of opening L1/L2 ECC of Cortex-A72 0

    1142 views
    2 replies
    Latest over 2 years ago
    by zhuhuaiyun
  • Answered

    Any global register in ARMv8? 0

    • AArch64
    • Armv8-A
    1436 views
    2 replies
    Latest over 2 years ago
    by zy_cloud
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone