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Query suggestions on GIC registers accessing latency

XF Wei

We need to have some sensible timeout defined in system developing work, as a result we want to know what is the maximum latency for a valid writing to GIC distributor registers(guaranteed to be visible to all logical components of the GIC architecture, including the CPU interace)? May I know if there are any reference data or document? Thanks

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    There's no simple answer to a question like that, a lot would depend on the SoC and what was happening at the time. Rather than relying on a timeout, why wouldn't you use the RWP (register write pending) bits to determine when an access (+it's side effects) have finished?

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    There's no simple answer to a question like that, a lot would depend on the SoC and what was happening at the time. Rather than relying on a timeout, why wouldn't you use the RWP (register write pending) bits to determine when an access (+it's side effects) have finished?

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