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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3611 Questions
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  • Suggested Answer

    APB 0

    • APB
    296 views
    1 reply
    Latest 2 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Is it normal that DC CVAC does also carry out a cache line invalidate on Cortex-A53? 0

    • Cache coherency
    501 views
    2 replies
    Latest 2 months ago
    by Mario Trams
  • Answered

    Cortex-R52+ mode switch 0

    • Cortex-R52+
    525 views
    3 replies
    Latest 2 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    More details on CSV2 0

    • Security
    • Branch Prediction
    765 views
    1 reply
    Latest 2 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Unable to write to memory region marked as both writable and executable on cortex-R82 0

    • Cortex-R82
    • Memory Architecture
    633 views
    5 replies
    Latest 3 months ago
    by HamzaF
  • Not Answered

    M0 GPIO level-sensitive interrupt, how many minimal CPU cycles? 0

    • Cortex-M0
    • Interrupt Handling
    222 views
    0 replies
    Started 3 months ago
    by Liudr
  • Suggested Answer

    Number of outstanding transactions in AXI 0

    • performance
    • AXI4
    • interconnect
    637 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Correctly invalidating Cortex-A53 shared L2 cache for access through ACP? +1

    • Cortex-A53
    • Cache coherency
    • AXI4
    • Cache Management
    • Cache Architecture
    665 views
    2 replies
    Latest 3 months ago
    by Dylan Barrie
  • Suggested Answer

    clarifications about ARCACHE bits in AXI4 0

    684 views
    2 replies
    Latest 3 months ago
    by Srilakshmi beeram
  • Answered

    Shift right instruction 0

    • AArch64
    612 views
    2 replies
    Latest 3 months ago
    by Eduard Kachalov
  • Not Answered

    How to implement divide with MVE intrinsic (Cortex M85) 0

    • Helium
    • MVE Intrinsics
    • Armv8.1-M
    367 views
    1 reply
    Latest 3 months ago
    by fjpmbb
  • Suggested Answer

    The behaviour of writenosnp and readnosnp that require request order in CHI 0

    503 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    axi ID problem 0

    409 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    what is difference between read unique and clean unique? 0

    442 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Setting up cache coherent transactions using CCI-500 0

    • Cortex-A72
    • Cache coherency
    • ACE
    • ACE-Lite
    • CoreLink CCI-500 Cache Coherent Interconnect
    427 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    retry problem 0

    • AMBA 5 CHI
    434 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Dynamic Core Management via Arm's PSCI on OdroidC4 0

    • Kernel Developers
    • smp
    • ODroid
    • cpu
    • psci
    • Software Development
    345 views
    0 replies
    Started 3 months ago
    by Michael Mospan
  • Suggested Answer

    timing diagram 0

    • AMBA 5 CHI
    667 views
    3 replies
    Latest 3 months ago
    by Ben Hicks Arm Employee Badge
  • Answered

    DMA Controller PL230 - Representation of PL230_DMA_CHNL_BITS 0

    • Architecture
    • DMA Devices
    • PrimeCell µDMAController (PL230)
    552 views
    2 replies
    Latest 4 months ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    How to Modify RME Register Values and the LEGACYTZEN Signal on ARM V3AE CPU 0

    • Security
    • Development Boards
    445 views
    1 reply
    Latest 4 months ago
    by Peter Harris Arm Employee Badge
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