AHB Write Access With wait states

When posing a question like this it helps if you can explain the specific area you are curious about so we can focus on your actual concern, rather than have to look at every possible point..

For this question there isn't anything I can see that looks wrong, so trying to guess what you are concerned about I am assuming it is HBURST changing from SINGLE to unknown during the waited write transfer data phase ?

The AHB manager is allowed to change all control signals (including HBURST) during a waited IDLE transfer, mainly so it can move from an IDLE to a NONSEQ transfer (see spec section 3.7.1), but what you show might happen if internally the manager is preparing for its next transfer and knows that next transfer will not be a SINGLE, or it might just be the manager design reverting to default values on all it's control outputs.

But regardless of why HBURST changed at this point, no AHB subordinate will have sampled any controls as HREADYOUT is low, so the HTRANS=IDLE/HBURST=SINGLE transfer combinationj was never seen by the system.

The only other things I can think of that might be concerning you is all the signals showing greyed-out "unknown" values, but this is usually just so we focus on the specific transfer we want to look at (the waited write transfer address and data phases). All the other signals WILL have kown values before and after the write transfer as AHB does not allow undriven outputs, but we don't care about those other values for the purpose of this diagram.

It might also be worth asking the originator of the IP that produced these outputs, or whoever created the diagram, as to what they were trying to demonstrate. Or if it's Arm IP, list where the diagram came from.

When posing a question like this it helps if you can explain the specific area you are curious about so we can focus on your actual concern, rather than have to look at every possible point..

For this question there isn't anything I can see that looks wrong, so trying to guess what you are concerned about I am assuming it is HBURST changing from SINGLE to unknown during the waited write transfer data phase ?

The AHB manager is allowed to change all control signals (including HBURST) during a waited IDLE transfer, mainly so it can move from an IDLE to a NONSEQ transfer (see spec section 3.7.1), but what you show might happen if internally the manager is preparing for its next transfer and knows that next transfer will not be a SINGLE, or it might just be the manager design reverting to default values on all it's control outputs.

But regardless of why HBURST changed at this point, no AHB subordinate will have sampled any controls as HREADYOUT is low, so the HTRANS=IDLE/HBURST=SINGLE transfer combinationj was never seen by the system.

The only other things I can think of that might be concerning you is all the signals showing greyed-out "unknown" values, but this is usually just so we focus on the specific transfer we want to look at (the waited write transfer address and data phases). All the other signals WILL have kown values before and after the write transfer as AHB does not allow undriven outputs, but we don't care about those other values for the purpose of this diagram.

It might also be worth asking the originator of the IP that produced these outputs, or whoever created the diagram, as to what they were trying to demonstrate. Or if it's Arm IP, list where the diagram came from.