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Does TCM configured as Strongly ordered memory have alignment alignment requirements?

Aswin Sankar

Hi experts,

I've been studying the ARM Cortex-R5 Technical Reference Manual and I have some questions about memory region configurations, specifically regarding strongly ordered memory regions.

To clarify, I'd like to know:

1. Do the alignment requirements for strongly ordered memory regions, such as RAM, also apply to Tightly Coupled Memory (TCM)?

2. Are there any specific alignment requirements for TCM when it is configured as strongly ordered?

3. Could you please explain the alignment requirements for strongly ordered memory regions in general, as I want to ensure I understand the concept correctly?

Additionally, I've observed a specific behavior that I'd like to understand:

When I configure OCram (On-Chip RAM) as Strongly Ordered (SO) and perform an unaligned access, a data abort occurs.
However, when I configure TCM as SO and perform an unaligned access, no data abort occurs.
This seems to suggest that the alignment requirements for strongly ordered memory regions may not be enforced in the same way for TCM as they are for OCram.

Could you please help me understand the reasons behind this difference in behavior between OCram and TCM, and provide clarification on the alignment requirements for strongly ordered memory regions in general?

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  • 0 Arm Employee Badge in reply to Aswin Sankar
    Aswin Sankar said:

    So if I put TCM as cached, would that really be cached ? 

    No, the TCMs always behave as Normal + non-cacheable.  TCM (tightly couple memories) are expected to be closely tied to the core, therefore the benefit you'd get from caches would (typically) be reduced.

    Aswin Sankar said:
    Does the above statement also include properties like cacheability and shareability?

    Shareability is an interesting one, it usually affects how cache coherency is maintained and the scope of barriers.  TCMs are private memories to the core, and in the case of the Cortex-R5, not cached - so the cache coherency aspect is kind of moot.  The section which talks about how MPU attributes are applied to TCMs doesn't mention share ability, so I'd assume those are taken from the MPU region.

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  • 0 Arm Employee Badge in reply to Aswin Sankar
    Aswin Sankar said:

    So if I put TCM as cached, would that really be cached ? 

    No, the TCMs always behave as Normal + non-cacheable.  TCM (tightly couple memories) are expected to be closely tied to the core, therefore the benefit you'd get from caches would (typically) be reduced.

    Aswin Sankar said:
    Does the above statement also include properties like cacheability and shareability?

    Shareability is an interesting one, it usually affects how cache coherency is maintained and the scope of barriers.  TCMs are private memories to the core, and in the case of the Cortex-R5, not cached - so the cache coherency aspect is kind of moot.  The section which talks about how MPU attributes are applied to TCMs doesn't mention share ability, so I'd assume those are taken from the MPU region.

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