We occasionally find in simulations that when the processor returns to normal from sleeping, or when an interrupt is nested in multiple layers and exits, the core's prefetching module u_cm7_pfu will issue an illegal address 0x3f_ffe8, and then the AXI matrix will reply with a RESEP=2'b11 In the above process, we have already disabled the cache function of the core. And we believe it has nothing to do with our software program. Preliminary suspicion is that the hardware design of the root's core is related.
The previous text refers to RRESP=2'b11