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I am working with the AM62A7 device, which has four A53 cores with 32 KB of L1D and L1I cache each, and a shared 512 KB L2 cache across all four cores. I am trying to perform an error-injection test for the cache memories to satisfy a safety requirement.
The error injection can be performed using the SoC ECC aggregator. However, once an error is injected, a cache access must occur at the injected location to trigger the ECC error.
Question:
1. Is there any known or validated method to perform a self-test for A53 cache memories (L1D, L1I, and L2 cache)?2. Is there any reference example or test code available that I can use as a starting point?
Regards,Nihar Potturu