Case 1: Usually, a matrix's HREADYMUXM0 signal is connected to the slave's hreadyin, which is recommended by ARM. As shown in Figure 1 below.
Case 2: But in some cases, such as when I want to optimize the backend timing, can I connect a slave's hreadyout back to my own hreadyin without using the matrix output HREADYMUXM0. As shown in Figure 2.
Question: If I connect according to Figure 2, will the access functional timing sequence sequences of the entire matrix become abnormal? will the timing sequence of the slave's functions has become abnormal? Or is there any problem happening?